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| MC68HC708XL36/d MC68HC708XL36 hcmos microcontroller unit technical data c8 h f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . .
f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ? motorola, inc., 1996 MC68HC708XL36 motorola list of sections 3 \ list of sections list of sections table of contents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 random access memory (ram) . . . . . . . . . . . . . . . . . . 33 nonvolatile memory (eprom) . . . . . . . . . . . . . . . . . . . . 35 configuration register (config). . . . . . . . . . . . . . . . . . 39 central processor unit (cpu) . . . . . . . . . . . . . . . . . . . . . 41 resets and interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 clock generator module (cgm). . . . . . . . . . . . . . . . . . 83 direct memory access module (dma) . . . . . . . . . . . . 111 break module (brk) . . . . . . . . . . . . . . . . . . . . . . . . . . . 149 monitor rom (mon) . . . . . . . . . . . . . . . . . . . . . . . . . . . 157 timer interface module (tim) . . . . . . . . . . . . . . . . . . . . 171 serial peripheral interface module (spi) . . . . . . . . . . . 201 serial communications interface module (sci). . . . . 235 input/output ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 283 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . list of sections MC68HC708XL36 4 list of sections motorola computer operating properly module (cop) . . . . . . 305 external interrupt module (irq) . . . . . . . . . . . . . . . . . . 311 keyboard interrupt module (kb) . . . . . . . . . . . . . . . . . 321 low-voltage inhibit module (lvi) . . . . . . . . . . . . . . . . 329 specifications. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 333 glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 351 index. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 literature updates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC708XL36 motorola table of contents 5 table of contents table of contents introduction contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 pin functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 memory map contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 unimplemented memory locations . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 reserved memory locations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 input/output (i/o) section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 ram contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 eprom contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 eprom control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 eprom programming sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 config register contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents MC68HC708XL36 6 table of contents motorola cpu contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 cpu registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 cpu during break interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 resets and interrupts contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 low-power modes contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 central processor unit (cpu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 clock generator module (cgm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 break module (brk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 computer operating properly module (cop) . . . . . . . . . . . . . . . . . . .76 direct memory access module (dma) . . . . . . . . . . . . . . . . . . . . . . . .76 external interrupt module (irq) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 keyboard interrupt module (kb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 low-voltage inhibit module (lvi) . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 serial communications interface module (sci) . . . . . . . . . . . . . . . . .78 serial peripheral interface module (spi) . . . . . . . . . . . . . . . . . . . . . . .79 timer interface module (tim) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 exiting wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 exiting stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 cgm contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 cgm registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents MC68HC708XL36 motorola table of contents 7 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 cgm during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 acquisition/lock time specifications . . . . . . . . . . . . . . . . . . . . . . . .106 dma contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .111 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130 dma during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 dma registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 brk contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153 break module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153 mon contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158 security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169 tim contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .171 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183 low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184 tim during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents MC68HC708XL36 8 table of contents motorola spi contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .201 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204 transmission formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208 queuing transmission data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213 error conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221 resetting the spi. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222 low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223 spi during break interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228 sci contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .235 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238 low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261 sci during break module interrupts . . . . . . . . . . . . . . . . . . . . . . . . .262 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263 i/o ports contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .283 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284 port a. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286 port b. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .288 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292 port e. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .294 port f. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297 port g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300 port h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents MC68HC708XL36 motorola table of contents 9 cop contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307 cop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309 monitor mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309 low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309 cop module during break interrupts . . . . . . . . . . . . . . . . . . . . . . . .310 irq contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .312 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .312 low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317 irq module during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . .318 irq status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . .318 kbi contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323 keyboard initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325 low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .326 keyboard module during break interrupts . . . . . . . . . . . . . . . . . . . .326 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .327 lvi contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .330 lvi status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .331 lvi interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332 low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . table of contents MC68HC708XL36 10 table of contents motorola specifications contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .333 preliminary electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . .333 mechanical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347 glossary glossary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .351 index index . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .363 literature updates literature distribution centers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .371 mfax. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .372 motorola sps world marketing world wide web server . . . . . . . . .372 csic microcontroller divisions web site . . . . . . . . . . . . . . . . . . . . .372 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC708XL36 motorola introduction 11 introduction introduction contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 mcu block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 pin assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 pin functions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 power supply pins (vdd and vss) . . . . . . . . . . . . . . . . . . . . . . . .17 oscillator pins (osc1 and osc2) . . . . . . . . . . . . . . . . . . . . . . . . .18 external reset pin (rst) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 external interrupt pins (irq1/vpp and irq2) . . . . . . . . . . . . . . . .18 clock ground pin (cgnd/evss) . . . . . . . . . . . . . . . . . . . . . . . . . .18 cgm power supply pin (vdda) . . . . . . . . . . . . . . . . . . . . . . . . . . .18 external filter capacitor pin (cgmxfc) . . . . . . . . . . . . . . . . . . . .18 port a input/output (i/o) pins (pa7Cpa0) . . . . . . . . . . . . . . . . . . .19 port b i/o pins (pb7Cpb0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 port c i/o pins (pc7Cpc0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 port d i/o pins (pd7/kbd7Cpd0/kbd0) . . . . . . . . . . . . . . . . . . . .19 port e i/o pins (pe7/tch3Cpe0) . . . . . . . . . . . . . . . . . . . . . . . . . .19 port f i/o pins (pf5Cpf0/ss) . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 port g i/o pins (pg3Cpg0) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 port h i/o pins (ph3Cph0). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 1-intro_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . introduction MC68HC708XL36 12 introduction motorola features features of the MC68HC708XL36 include the following: ? high-performance m68hc08 architecture ? fully upward-compatible object code with m6805, m146805, and m68hc05 families ? 8-mhz internal bus frequency ? 36 kbytes of on-chip erasable programmable read-only memory (eprom) or one-time programmable read-only memory (otprom) ? on-chip programming firmware for use with host personal computer ? eprom/otprom data security ? one kbyte of on-chip random-access memory (ram) ? serial peripheral interface module (spi) ? serial communications interface module (sci) ? 16-bit, 4-channel timer interface module (tim) ? three-channel direct memory access module (dma) ? clock generator module (cgm) ? system protection features C optional computer operating properly (cop) reset C low-voltage detection with optional reset C illegal opcode detection with optional reset C illegal address detection with optional reset ? 56-pin plastic shrink dual-in-line package (sdip) or 64-pin plastic quad flat pack (qfp) ? low-power design (fully static with stop and wait modes) ? master reset pin and power-on reset ? 8-bit keyboard wakeup port 2-intro_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . introduction mcu block diagram MC68HC708XL36 motorola introduction 13 features of the cpu08 include the following: ? enhanced hc05 programming model ? extensive loop control functions ? 16 addressing modes (eight more than the hc05) ? 16-bit index register and stack pointer ? memory-to-memory data transfers ? fast 8 8 multiply instruction ? fast 16/8 divide instruction ? binary-coded decimal (bcd) instructions ? optimization for controller applications ? third party c language support mcu block diagram figure 1 shows the structure of the MC68HC708XL36. 3-intro_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . introduction MC68HC708XL36 14 introduction motorola figure 1. mcu block diagram break module clock generator module system integration module direct memory access module serial communications serial peripheral timer interface module low-voltage inhibit module power-on reset module keyboard arithmetic/logic unit (alu) cpu registers m68hc08 cpu control and status registers 88 bytes user eprom 36,864 bytes user ram 1024 bytes monitor rom 240 bytes user eprom vector space 32 bytes irq module power porta ddra ddrb portb ddrc portc ddrd portd ddre porte portf ddrf portg porth ddrg ddrh internal bus osc1 osc2 cgmxfc rst irq1/v pp irq2 v ss v dd v dda cgnd/ev ss interface module interface module interrupt module computer operating properly module pa7Cpa0 pb7Cpb0 pc7Cptc0 pd7/kbd7Cpd0/kbd0 pe7/tch3 pe6/tch2 pe5/tch1 pe4/tch0 pe3/tclk pe2/txd pe1/rxd pe0 pf5 pf4 pf3/miso pf1/spsck pf0/ ss pf2/mosi pg3Cpg0 (64-pin package only) ph3Cph0 (64-pin package only) 4-intro_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . introduction pin assignments MC68HC708XL36 motorola introduction 15 pin assignments figure 2. sdip pin assignments rst 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 irq1/v pp irq2 v dda cgmxfc osc1 osc2 v ss v dd pa0 pa1 pa2 pa3 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb3 pb4 pb5 pb6 pb7 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 pd0/ kbd0 pd1/ kbd1 pd2/ kbd2 pd3/ kbd3 pd4/ kbd4 pd5/ kbd5 pd6/ kbd6 pd7/ kbd7 pe0 pe1/rxd pe2/txd pe3/tclk pe4/tch0 pe5/tch1 pe6/tch2 pe7/tch3 pf0/ ss pf1/spsck cgnd/ev ss pf2/mosi pf3/miso pf4 pf5 5-intro_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . introduction MC68HC708XL36 16 introduction motorola figure 3. qfp pin assignments note: ports g and h are available only with the qfp. pa3 ph1 pe0 pa2 pa1 pa0 v dd v ss osc2 osc1 pa4 pa5 pa6 pa7 pb0 pb1 pb2 pb3 pe7/tch3 pe6/tch2 pe5/tch1 pe4/tch0 pe3/tclk pe2/txd pe1/rxd pd7/kbd7 pd6/ kbd6 pd5/ kbd5 pd4/ kbd4 pd3/kbd3 pd2/ kbd2 pd1/ kbd1 pd0/ kbd0 ph0 pf5 pf4 pf3/miso pf2/mosi cgnd/ev ss pf1/spsck pf0/ ss cgmxfc v dda irq2 irq1/v pp rst ph3 ph2 pb6 pb4 pb5 pb7 pg0 pg1 pg2 pg3 pc0 pc1 pc2 pc3 pc4 pc5 pc6 pc7 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 6-intro_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . introduction pin functions MC68HC708XL36 motorola introduction 17 pin functions power supply pins (v dd and v ss ) v dd and v ss are the power supply and ground pins. the mcu operates from a single power supply. fast signal transitions on mcu pins place high, short-duration current demands on the power supply. to prevent noise problems, take special care to provide power supply bypassing at the mcu as figure 4 shows. place the c1 bypass capacitor as close to the mcu as possible. use a high-frequency-response ceramic capacitor for c1. c2 is an optional bulk current bypass capacitor for use in applications that require the port pins to source high current levels. figure 4. power supply bypassing mcu v dd c2 c1 0.1 m f v ss v dd + note: component values shown represent typical applications. 7-intro_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . introduction MC68HC708XL36 18 introduction motorola oscillator pins (osc1 and osc2) the osc1 and osc2 pins are the connections for the on-chip oscillator circuit. (see clock generator module on page 83.) external reset pin ( rst) a logic 0 on the rst pin forces the mcu to a known startup state. rst is bidirectional, allowing a reset of the entire system. it is driven low when any internal reset source is asserted. external interrupt pins ( irq1/v pp and irq2) irq1/v pp and irq2 are asynchronous external interrupt pins. (see external interrupt module on page 311.) irq1/v pp is also the eprom/otprom programming power pin. (see memory map on page 21.) clock ground pin (cgnd/ev ss ) cgnd/ev ss is the ground for the port output buffers and the ground return for the serial clock in the serial peripheral interface module (spi). (see serial peripheral interface module on page 201.) note: cgnd/ev ss must be grounded for proper mcu operation. cgm power supply pin (v dda ) v dda is the power supply pin for the analog portion of the clock generator module (cgm). (see clock generator module on page 83.) external filter capacitor pin (cgmxfc) cgmxfc is an external filter capacitor connection for the cgm. (see clock generator module on page 83.) 8-intro_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . introduction pin functions MC68HC708XL36 motorola introduction 19 port a input/output (i/o) pins (pa7Cpa0) pa7Cpa0 are general-purpose bidirectional i/o port pins. (see input/output ports on page 283.) port b i/o pins (pb7Cpb0) pb7Cpb0 are general-purpose bidirectional i/o port pins. (see input/output ports on page 283.) port c i/o pins (pc7Cpc0) pc7Cpc0 are general-purpose bidirectional i/o port pins. (see input/output ports on page 283.) port d i/o pins ( pd7/ kbd7C pd0/ kbd0) pd7/ kbd7C pd0/ kbd0 are general-purpose bidirectional i/o port pins. any or all of the port d pins can be programmed to serve as external interrupt pins. (see input/output ports on page 283.) port e i/o pins (pe7/tch3Cpe0) port e is an 8-bit special function port that shares five of its pins with the timer interface module (tim) and two of its pins with the serial communications interface (sci) module. (see timer interface module , serial communications interface module , and input/output ports .) port f i/o pins (pf5Cpf0/ ss) port f is a 6-bit special function port that shares four of its pins with the serial peripheral interface module (spi). (see serial peripheral interface module and input/output ports .) 9-intro_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . introduction MC68HC708XL36 20 introduction motorola port g i/o pins (pg3Cpg0) pg3Cpg0 are general-purpose bidirectional i/o pins. (see input/output ports on page 283.) port g is available only with the 64-pin package. port h i/o pins (ph3Cph0) ph3Cph0 are general-purpose bidirectional i/o pins. (see input/output ports on page 283.) port h is available only with the 64-pin package. 10-intro_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC708XL36 motorola memory map 21 memory map memory map contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 unimplemented memory locations . . . . . . . . . . . . . . . . . . . . . . . . . . .22 reserved memory locations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 input/output (i/o) section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 1-mem_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map MC68HC708XL36 22 memory map motorola introduction the cpu08 can address 64 kbytes of memory space. the memory map, shown in figure 1 , includes: ? 36 kbytes of erasable programmable read-only memory (eprom) ? one kbyte of random-access memory (ram) ? 34 bytes of user-defined vectors ? 240 bytes of monitor rom unimplemented memory locations accessing an unimplemented location can cause an illegal address reset if illegal address resets are enabled. in the memory map figure and in register figures in this document, unimplemented locations are shaded. reserved memory locations accessing a reserved location can have unpredictable effects on mcu operation. in the memory map figure and in register figures in this document, reserved locations are marked with the word reserved or with the letter r. 2-mem_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map reserved memory locations MC68HC708XL36 motorola memory map 23 $0000 i/o registers 80 bytes $004f $0050 ram 1024 bytes $044f unimplemented 27,056 bytes $0450 $6dff $6e00 eprom 36,864 bytes $fdff $fe00 break status register (bsr) $fe01 reset status register (rsr) $fe02 reserved $fe03 break flag control register (bfcr) $fe04 interrupt status register 1 (int1) $fe05 interrupt status register 2 (int2) $fe06 interrupt status register 3 (int3) $fe07 eprom control register (epmcr) unimplemented 4 bytes $fe08 $fe0b $fe0c break address register high (brkh) $fe0d break address register low (brkl) $fe0e break status and control register (bscr) $fe0f lvi status register (lvisr) $fe10 monitor rom 240 bytes $feff unimplemented 222 bytes $ff00 $ffdd $ffde vectors 34 bytes $ffff figure 1. memory map 3-mem_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map MC68HC708XL36 24 memory map motorola input/output (i/o) section addresses $0000C$004f contain most of the control, status, and data registers. additional i/o registers have the following addresses: ? $fe00 (break status register, bsr) ? $fe01 (reset status register, rsr) ? $fe03 (break flag control register, bfcr) ? $fe04 (interrupt status register 1, int1) ? $fe05 (interrupt status register 2, int2) ? $fe06 (interrupt status register 3, int3) ? $fe07 (eprom control register, epmcr) ? $fe0c and $fe0d (break address registers, brkh and brkl) ? $fe0e (break status and control register, bscr) ? $fe0f (lvi status register, lvisr) ? $ffff (cop control register, copctl) 4-mem_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map input/output (i/o) section MC68HC708XL36 motorola memory map 25 register name addr. bit 7 654321 bit 0 port a data register (porta) $0000 read: pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 write: reset: unaffected by reset port b data register (portb) $0001 read: pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 write: reset: unaffected by reset port c data register (portc) $0002 read: pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 write: reset: unaffected by reset port d data register (portd) $0003 read: pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 write: reset: unaffected by reset data direction register a (ddra) $0004 read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset: 00000000 data direction register b (ddrb) $0005 read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset: 00000000 data direction register c (ddrc) $0006 read: ddrc7 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset: 00000000 data direction register d (ddrd) $0007 read: ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset: 00000000 port e data register (porte) $0008 read: pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 write: reset: unaffected by reset port f data register (portf) $0009 read: 0 0 pf5 pf4 pf3 pf2 pf1 pf0 write: reset: unaffected by reset port g data register (portg) $000a read: 0000 pg3 pg2 pg1 pg0 write: reset: unaffected by reset port h data register (porth) $000b read: 0000 ph3 ph2 ph1 ph0 write: reset: unaffected by reset data direction register e (ddre) $000c read: ddre7 ddre6 ddre5 ddre4 ddre3 ddre2 ddre1 ddre0 write: reset: 00000000 data direction register f (ddrf) $000d read: 0 0 ddrf5 ddrf4 ddrf3 ddrf2 ddrf1 ddrf0 write: reset: 00000000 = unimplemented r = reserved figure 2. i/o register summary 5-mem_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map MC68HC708XL36 26 memory map motorola data direction register g (ddrg) $000e read: 0000 ddrg3 ddrg2 ddrg1 ddrg0 write: reset: 00000000 data direction register h (ddrh) $000f read: 0000 ddrh3 ddrh2 ddrh1 ddrh0 write: reset: 00000000 spi control register (spcr) $0010 read: sprie dmas spmstr cpol cpha spwom spe sptie write: reset: 00100000 spi status and control register (spscr) $0011 read: sprf errie ovrf modf spte modfen spr1 spr0 write: reset: 00001000 spi data register (spdr) $0012 read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset sci control register 1 (scc1) $0013 read: loops ensci txinv m wake ilty pen pty write: reset: 00000000 sci control register 2 (scc2) $0014 read: sctie tcie scrie ilie te re rwu sbk write: reset: 00000000 sci control register 3 (scc3) $0015 read: r8 t8 dmare dmate orie neie feie peie write: reset: u u 000000 sci status register 1 (scs1) $0016 read: scte tc scrf idle or nf fe pe write: reset: 11000000 sci status register 2 (scs2) $0017 read: bkf rpf write: reset: 00000000 sci data register (scdr) $0018 read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset sci baud rate register (scbr) $0019 read: scp1 scp0 r scr2 scr1 scr0 write: reset: 00000000 keyboard status and control register (kbscr) $001a read: 0000 keyf 0 imaskk modek write: ackk reset: 00000000 keyboard interrupt enable register (kbier) $001b read: kbie7 kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset: 00000000 register name addr. bit 7 654321 bit 0 = unimplemented r = reserved figure 2. i/o register summary (continued) 6-mem_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map input/output (i/o) section MC68HC708XL36 motorola memory map 27 pll control register (pctl) $001c read: pllie pllf pllon bcs 1111 write: reset: 00101111 pll bandwidth control register (pbwc) $001d read: auto lock a cq xld 0000 write: reset: 00000000 pll programming register (ppg) $001e read: mul7 mul6 mul5 mul4 vrs7 vrs6 vrs5 vrs4 write: reset: 01100110 con?guration register (config) $001f read: coprs lvistop lvirstd lvipwrd ssrec 0 stop copd write: reset: 00000000 tim status and control register (tsc) $0020 read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset: 00100000 tim dma select register (tdma) $0021 read: 0000 dma3s dma2s dma1s dma0s write: reset: 00000000 tim counter register high (tcnth) $0022 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 00000000 tim counter register low (tcntl $0023 read: bit 7 654321 bit 0 write: reset: 00000000 tim counter modulo reg. high (tmodh) $0024 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 11111111 tim counter modulo reg. low (tmodl) $0025 read: bit 7 654321 bit 0 write: reset: 11111111 tim channel 0 status and control register (tsc0) $0026 read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset: 00000000 tim channel 0 register high (tch0h) $0027 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset tim channel 0 register low (tch0l) $0028 read: bit 7 654321 bit 0 write: reset: indeterminate after reset tim channel 1 status and control register (tsc1) $0029 read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset: 00000000 register name addr. bit 7 654321 bit 0 = unimplemented r = reserved figure 2. i/o register summary (continued) 7-mem_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map MC68HC708XL36 28 memory map motorola tim channel 1 register high (tch1h) $002a read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset tim channel 1 register low (tch1l) $002b read: bit 7 654321 bit 0 write: reset: indeterminate after reset tim channel 2 status and control register (tsc2) $002c read: ch2f ch2ie ms2b ms2a els2b els2a tov2 ch2max write: 0 reset: 00000000 tim channel 2 register high (tch2h) $002d read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset tim channel 2 register low (tch2l) $002e read: bit 7 654321 bit 0 write: reset: indeterminate after reset tim channel 3 status and control register (tsc3) $002f read: ch3f ch3ie 0 ms3a els3b els3a tov3 ch3max write: 0 reset: 00000000 tim channel 3 register high (tch3h) $0030 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset tim channel 3 register low (tch3l) $0031 read: bit 7 654321 bit 0 write: reset: indeterminate after reset irq status and control register (iscr) $0032 read: irqf2 0 imask2 mode2 irqf1 0 imask1 mode1 write: ack2 ack1 reset: 00000000 $0033 reserved dma channel 0 source address register high) (d0sh) $0034 read: ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 write: reset: indeterminate after reset dma channel 0 source address register low (d0sl) $0035 read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: reset: indeterminate after reset dma channel 0 destination address register high (d0dh) $0036 read: ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 write: reset: indeterminate after reset dma channel 0 destination address register low (d0dl) $0037 read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: reset: indeterminate after reset register name addr. bit 7 654321 bit 0 = unimplemented r = reserved figure 2. i/o register summary (continued) 8-mem_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map input/output (i/o) section MC68HC708XL36 motorola memory map 29 dma channel 0 control register (d0c) $0038 read: sdc3 sdc2 sdc1 sdc0 bwc dts2 dts1 dts0 write: reset: indeterminate after reset dma channel 0 block length register (d0bl) $0039 read: bl7 bl6 bl5 bl4 bl3 bl2 bl1 bl0 write: reset: indeterminate after reset $003a reserved dma channel 0 byte count register (d0bc) $003b read: bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 write: reset: 00000000 dma channel 1 source address register high) (d1sh) $003c read: ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 write: reset: indeterminate after reset dma channel 1 source address register low (d1sl) $003d read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: reset: indeterminate after reset dma channel 1 destination address register high (d1dh) $003e read: ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 write: reset: indeterminate after reset dma channel 1 destination address register low (d1dl) $003f read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: reset: indeterminate after reset dma channel 1 control register (d1c) $0040 read: sdc3 sdc2 sdc1 sdc0 bwc dts2 dts1 dts0 write: reset: indeterminate after reset dma channel 1 block length register (d1bl) $0041 read: bl7 bl6 bl5 bl4 bl3 bl2 bl1 bl0 write: reset: indeterminate after reset $0042 reserved dma channel 1 byte count register (d1bc) $0043 read: bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 write: reset: 00000000 dma channel 2 source address register high) (d2sh) $0044 read: ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 write: reset: indeterminate after reset dma channel 2 source address register low (d2sl) $0045 read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: reset: indeterminate after reset register name addr. bit 7 654321 bit 0 = unimplemented r = reserved figure 2. i/o register summary (continued) 9-mem_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map MC68HC708XL36 30 memory map motorola dma channel 2 destination address register high (d2dh) $0046 read: ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 write: reset: indeterminate after reset dma channel 2 destination address register low (d2dl) $0047 read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: reset: indeterminate after reset dma channel 2 control register (d2c) $0048 read: sdc3 sdc2 sdc1 sdc0 bwc dts2 dts1 dts0 write: reset: indeterminate after reset dma channel 2 block length register (d2bl) $0049 read: bl7 bl6 bl5 bl4 bl3 bl2 bl1 bl0 write: reset: indeterminate after reset $004a reserved dma channel 2 byte count register (d2bc) $004b read: bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 write: reset: 00000000 dma control register 1 (dc1) $004c read: bb1 bb0 tec2 iec2 tec1 iec1 tec0 iec0 write: reset: 00000000 dma status and control register (dsc) $004d read: dmap l2 l1 l0 dmawe ifc2 ifc1 ifc0 write: reset: 00000000 dma control register 2 (dc2) $004e read: swi7 swi6 swi5 swi4 swi3 swi2 swi1 swi0 write: reset: 00000000 $004f reserved break status register (bsr) $fe00 read: rrrrrr bw r write: clear bw reset: 0 reset status register (rsr) $fe01 read: por pin cop ilop ilad 0 lvi 0 write: reset: 10000000 break flag control register (bfcr) $fe03 read: bcfe rrrrrrr write: reset: 0 interrupt status register 1 (int1) $fe04 read: if6 if5 if4 if3 if2 if1 0 0 write: rrrrrrrr reset: 00000000 register name addr. bit 7 654321 bit 0 = unimplemented r = reserved figure 2. i/o register summary (continued) 10-mem_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map input/output (i/o) section MC68HC708XL36 motorola memory map 31 interrupt status register 2 (int2) $fe05 read: if14 if13 if12 if11 if10 if9 if8 if7 write: rrrrrrrr reset: 00000000 interrupt status register 3 (int3) $fe06 read: 0000000 if15 write: rrrrrrrr reset: 00000000 eprom control register (epmcr) $fe07 read: r 0000 elat 0 epgm write: reset: 00000000 break address register high (brkh) $fe0c read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 00000000 break address register low (brkl) $fe0d read: bit 7 654321 bit 0 write: reset: 00000000 break status and control register (bscr) $fe0e read: brke brka 000000 write: reset: 00000000 lvi status register (lvisr) $fe0f read: lviout 0000000 write: reset: 00000000 cop control register (copctl) $ffff read: low byte of reset vector write: writing clears cop counter reset: unaffected by reset register name addr. bit 7 654321 bit 0 = unimplemented r = reserved figure 2. i/o register summary (continued) 11-mem_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . memory map MC68HC708XL36 32 memory map motorola table 1 is a list of vector locations. table 1. vector addresses address vector lower priority $ffde keyboard vector (high) $ffdf keyboard vector (low) $ffe0 irq2 vector (high) $ffe1 irq2 vector (low) $ffe2 sci transmit vector (high) $ffe3 sci transmit vector (low) $ffe4 sci receive vector (high) $ffe5 sci receive vector (low) $ffe6 sci error vector (high) $ffe7 sci error vector (low) $ffe8 spi transmit vector (high) $ffe9 spi transmit vector (low) $ffea spi receive vector (high) $ffeb spi receive vector (low) $ffec tim over?ow vector (high) $ffed tim over?ow vector (low) $ffee tim channel 3 vector (high) $ffef tim channel 3 vector (low) $fff0 tim channel 2 vector (high) $fff1 tim channel 2 vector (low) $fff2 tim channel 1 vector (high) $fff3 tim channel 1 vector (low) $fff4 tim channel 0 vector (high) $fff5 tim channel 0 vector (low) $fff6 dma vector (high) $fff7 dma vector (low) $fff8 pll vector (high) $fff9 pll vector (low) higher priority $fffa irq1 vector (high) $fffb irq1 vector (low) $fffc swi vector (high) $fffd swi vector (low) $fffe reset vector (high) $ffff reset vector (low) 12-mem_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC708XL36 motorola ram 33 random access memory ram contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 introduction this section describes the 1024 bytes of ram. functional description addresses $0050 through $044f are ram locations. the location of the stack ram is programmable. the 16-bit stack pointer allows the stack to be anywhere in the 64-kbyte memory space. note: for correct operation, the stack pointer must point only to ram locations. within page 0 are 176 bytes of ram. because the location of the stack ram is programmable, all page 0 ram locations can be used for i/o control and user data or code. when the stack pointer is moved from its reset location at $00ff, direct addressing mode instructions can access efficiently all page 0 ram locations. page 0 ram, therefore, provides ideal locations for frequently accessed global variables. before processing an interrupt, the cpu uses five bytes of the stack to save the contents of the cpu registers. 1-ram02_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . ram MC68HC708XL36 34 ram motorola note: for m6805 compatibility, the h register is not stacked. during a subroutine call, the cpu uses two bytes of the stack to store the return address. the stack pointer decrements during pushes and increments during pulls. note: be careful when using nested subroutines. the cpu may overwrite data in the ram during a subroutine or during the interrupt stacking operation. 2-ram02_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC708XL36 motorola eprom 35 nonvolatile memory eprom contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .35 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 eprom control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .37 eprom programming sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . .38 introduction this section describes the 36 kbytes of nonvolatile memory. 1-epm36k_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . eprom MC68HC708XL36 36 eprom motorola functional description an mcu with a quartz window has 36 kbytes of erasable, programmable rom (eprom). the quartz window allows eprom erasure by using ultraviolet light. an unprogrammed or erased location reads as $00. the following addresses are user eprom locations: ? $6e00C$fdff ? $ffe0C$ffff these locations are reserved for user-defined interrupt and reset vectors. programming tools are available from motorola. contact your local motorola representative for more information. note: a security feature discourages viewing of the eprom. 1 1. no security feature is absolutely secure. however, motorolas strategy is to make reading or copying the eprom difficult for unauthorized users. 2-epm36k_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . eprom eprom control register MC68HC708XL36 motorola eprom 37 eprom control register the eprom control register controls eprom programming. elat eprom latch control bit this read/write bit latches the address and data buses for programming the eprom. clearing elat also clears the epgm bit. eprom data cannot be read when elat is set. 1 = buses configured for eprom programming 0 = buses configured for normal operation epgm eprom program control bit this read/write bit applies the programming voltage from the irq1/v pp pin to the eprom. to write to the epgm bit, the elat bit must be set already. the stop instruction clears the epgm bit. reset also clears epgm. 1 = eprom programming power switched on 0 = eprom programming power switched off address: $fe07 bit 7 654321 bit 0 read: r 0000 elat 0 epgm write: reset: 00000000 = unimplemented r = reserved figure 1. eprom control register (epmcr) 3-epm36k_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . eprom MC68HC708XL36 38 eprom motorola eprom programming sequence use the following procedure to program a byte of eprom: 1. apply v pp to the irq1/v pp pin. 2. set the elat bit. note: writing logic 1s to both the elat and epgm bits with a single instruction sets only the elat bit. epgm must be set by a separate instruction in the programming sequence. 3. write to any user eprom address. note: writing to an invalid address prevents the programming voltage from being applied. 4. set the epgm bit. 5. wait for a time, t epgm . 6. clear the elat and epgm bits. 4-epm36k_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC708XL36 motorola config 39 configuration register config contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 introduction the configuration register controls the following options: ? operation of low-voltage inhibit module (lvi) during stop mode ? resets caused by the lvi ? power to the lvi ? stop mode recovery time (32 or 4096 cgmxclk cycles) ? cop timeout period (2 18 C 2 4 or 2 13 C 2 4 cgmxclk cycles) ? stop instruction ? operation of the computer operating properly module (cop) functional description the configuration register initializes certain mcu options and can be written only once after each reset. address: $001f bit 7 654321 bit 0 read: coprs lvistop lvirstd lvipwrd ssrec 0 stop copd write: reset: 00000000 = unimplemented figure 1. configuration register (config) 1-mor_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . config MC68HC708XL36 40 config motorola coprs cop rate select bit coprs selects the cop timeout period. reset clears coprs. 1 = cop timeout period = 2 13 C 2 4 cgmxclk cycles 0 = cop timeout period = 2 18 C 2 4 cgmxclk cycles lvistop lvi enable in stop mode bit when the lvipwrd bit is clear, setting the lvistop bit enables the lvi to operate during stop mode. reset clears lvistop. 1 = lvi enabled during stop mode 0 = lvi disabled during stop mode note: if the lvipwrd bit is at logic 0, the lvistop bit must be at logic 0 to meet the minimum stop mode i dd specification. lvirstd lvi reset disable bit when the lvipwrd bit is clear, setting the lvirstd bit disables the reset signal from the lvi module. reset clears lvrstd. 1 = lvi module reset disabled 0 = lvi module reset enabled lvipwrd lvi power disable bit lvipwrd disables lvi. reset clears lvipwrd. 1 = lvi power disabled 0 = lvi power enabled ssrec short stop recovery bit ssrec shortens stop mode recovery time from 4096 cgmxclk cycles to 32 cgmxclk cycles. reset clears ssrec. 1 = stop mode recovery after 32 cgmxclk cycles 0 = stop mode recovery after 4096 cgmxclk cycles note: do not set the ssrec bit if using an external crystal oscillator. stop stop instruction enable bit stop enables the stop instruction. reset clears stop. 1 = stop instruction enabled 0 = stop instruction treated as illegal opcode copd cop disable bit copd disables the cop module. reset clears copd. 1 = cop module disabled 0 = cop module enabled 2-mor_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC708XL36 motorola cpu 41 central processor unit cpu contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .41 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 cpu registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 index register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 stack pointer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 program counter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 condition code register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 arithmetic/logic unit (alu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48 cpu during break interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 instruction set summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 opcode map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .55 introduction the m68hc08 cpu is an enhanced and fully object-code-compatible version of the m68hc05 cpu. the cpu08 reference manual (motorola document number cpu08rm/ad) contains a description of the cpu instruction set, addressing modes, and architecture. 1-cpu8_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . cpu MC68HC708XL36 42 cpu motorola features features of the cpu include the following: ? object code fully upward-compatible with m68hc05 family ? 16-bit stack pointer with stack manipulation instructions ? 16-bit index register with x-register manipulation instructions ? 8-mhz cpu internal bus frequency ? 64-kbyte program/data memory space ? 16 addressing modes ? memory-to-memory data moves without using accumulator ? fast 8-bit by 8-bit multiply and 16-bit by 8-bit divide instructions ? enhanced binary-coded decimal (bcd) data handling ? modular architecture with expandable internal bus definition for extension of addressing range beyond 64 kbytes ? low-power stop and wait modes cpu registers figure 1 shows the five cpu registers. cpu registers are not part of the memory map. 2-cpu8_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . cpu cpu registers MC68HC708XL36 motorola cpu 43 figure 1. cpu registers accumulator the accumulator is a general-purpose 8-bit register. the cpu uses the accumulator to hold operands and the results of arithmetic/logic operations. accumulator (a) index register (h:x) stack pointer (sp) program counter (pc) condition code register (ccr) carry/borrow flag zero flag negative flag interrupt mask half-carry flag twos complement overflow flag v11hinzc h x 0 0 0 0 7 15 15 15 70 bit 7 654321 bit 0 read: write: reset: unaffected by reset figure 2. accumulator (a) 3-cpu8_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . cpu MC68HC708XL36 44 cpu motorola index register the 16-bit index register allows indexed addressing of a 64-kbyte memory space. h is the upper byte of the index register, and x is the lower byte. h:x is the concatenated 16-bit index register. in the indexed addressing modes, the cpu uses the contents of the index register to determine the conditional address of the operand. the index register can serve also as a temporary data storage location. stack pointer the stack pointer is a 16-bit register that contains the address of the next location on the stack. during a reset, the stack pointer is preset to $00ff. the reset stack pointer (rsp) instruction sets the least significant byte to $ff and does not affect the most significant byte. the stack pointer decrements as data is pushed onto the stack and increments as data is pulled from the stack. in the stack pointer 8-bit offset and 16-bit offset addressing modes, the stack pointer can function as an index register to access data on the stack. the cpu uses the contents of the stack pointer to determine the conditional address of the operand. bit 15 1413121110987654321 bit 0 read: write: reset: 00000000xxxxxxxx x = indeterminate figure 3. index register (h:x) bit 15 1413121110987654321 bit 0 read: write: reset: 0000000011111111 figure 4. stack pointer (sp) 4-cpu8_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . cpu cpu registers MC68HC708XL36 motorola cpu 45 note: the location of the stack is arbitrary and may be relocated anywhere in ram. moving the sp out of page 0 ($0000 to $00ff) frees direct address (page 0) space. for correct operation, the stack pointer must point only to ram locations. program counter the program counter is a 16-bit register that contains the address of the next instruction or operand to be fetched. normally, the program counter automatically increments to the next sequential memory location every time an instruction or operand is fetched. jump, branch, and interrupt operations load the program counter with an address other than that of the next sequential location. during reset, the program counter is loaded with the reset vector address located at $fffe and $ffff. the vector address is the address of the first instruction to be executed after exiting the reset state. bit 15 1413121110987654321 bit 0 read: write: reset: loaded with vector from $fffe and $ffff figure 5. program counter (pc) 5-cpu8_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . cpu MC68HC708XL36 46 cpu motorola condition code register the 8-bit condition code register contains the interrupt mask and five flags that indicate the results of the instruction just executed. bits 6 and 5 are set permanently to logic 1. the following paragraphs describe the functions of the condition code register. v overflow flag the cpu sets the overflow flag when a two's complement overflow occurs. the signed branch instructions bgt, bge, ble, and blt use the overflow flag. 1 = overflow 0 = no overflow h half-carry flag the cpu sets the half-carry flag when a carry occurs between accumulator bits 3 and 4 during an add-without-carry (add) or add-with-carry (adc) operation. the half-carry flag is required for binary-coded decimal (bcd) arithmetic operations. the daa instruction uses the states of the h and c flags to determine the appropriate correction factor. 1 = carry between bits 3 and 4 0 = no carry between bits 3 and 4 i interrupt mask when the interrupt mask is set, all maskable cpu interrupts are disabled. cpu interrupts are enabled when the interrupt mask is cleared. when a cpu interrupt occurs, the interrupt mask is set automatically after the cpu registers are saved on the stack, but before the interrupt vector is fetched. 1 = interrupts disabled 0 = interrupts enabled bit 7 654321 bit 0 read: v11hinzc write: reset: x 1 1 x 1 x x x x = indeterminate figure 6. condition code register (ccr) 6-cpu8_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . cpu cpu registers MC68HC708XL36 motorola cpu 47 note: to maintain m6805 compatibility, the upper byte of the index register (h) is not stacked automatically. if the interrupt service routine modifies h, then the user must stack and unstack h using the pshh and pulh instructions. after the i bit is cleared, the highest-priority interrupt request is serviced first. a return from interrupt (rti) instruction pulls the cpu registers from the stack and restores the interrupt mask from the stack. after any reset, the interrupt mask is set and can only be cleared by the clear interrupt mask software instruction (cli). n negative flag the cpu sets the negative flag when an arithmetic operation, logic operation, or data manipulation produces a negative result, setting bit 7 of the result. 1 = negative result 0 = non-negative result z zero flag the cpu sets the zero flag when an arithmetic operation, logic operation, or data manipulation produces a result of $00. 1 = zero result 0 = nonzero result c carry/borrow flag the cpu sets the carry/borrow flag when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. some instructions such as bit test and branch, shift, and rotate also clear or set the carry/borrow flag. 1 = carry out of bit 7 0 = no carry out of bit 7 7-cpu8_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . cpu MC68HC708XL36 48 cpu motorola arithmetic/logic unit (alu) the alu performs the arithmetic and logic operations defined by the instruction set. refer to the cpu08 reference manual (motorola document number cpu08rm/ad) for a description of the instructions and addressing modes and more detail about the architecture of the cpu. low-power modes the wait and stop instructions put the mcu in low power-consumption standby modes. wait mode the wait instruction: ? clears the interrupt mask (i bit) in the condition code register, enabling interrupts. after exit from wait mode by interrupt, the i bit remains clear. after exit by reset, the i bit is set. ? disables the cpu clock. stop mode the stop instruction: ? clears the interrupt mask (i bit) in the condition code register, enabling external interrupts. after exit from stop mode by external interrupt, the i bit remains clear. after exit by reset, the i bit is set. ? disables the cpu clock. after exiting stop mode, the cpu clock begins running after the oscillator stabilization delay. 8-cpu8_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . cpu cpu during break interrupts MC68HC708XL36 motorola cpu 49 cpu during break interrupts if the break module is enabled, a break interrupt causes the cpu to execute the software interrupt instruction (swi) at the completion of the current cpu instruction. (see break module on page 149.) the program counter vectors to $fffcC$fffd ($fefcC$fefd in monitor mode). if the break interrupt has been deasserted, a return-from-interrupt instruction (rti) in the break routine ends the break interrupt and returns the mcu to normal operation. instruction set summary table 1. instruction set summary source form operation description effect on ccr address mode opcode operand cycles vh i nzc adc # opr adc opr adc opr adc opr ,x adc opr ,x adc ,x adc opr ,sp adc opr ,sp add with carry a ? (a) + (m) + (c) C imm dir ext ix2 ix1 ix sp1 sp2 a9 b9 c9 d9 e9 f9 9ee9 9ed9 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 add # opr add opr add opr add opr ,x add opr ,x add ,x add opr ,sp add opr ,sp add without carry a ? (a) + (m) C imm dir ext ix2 ix1 ix sp1 sp2 ab bb cb db eb fb 9eeb 9edb ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ais # opr add immediate value (signed) to sp sp ? (sp) + (16 ? m) C C C C C C imm a7 ii 2 aix # opr add immediate value (signed) to h:x h:x ? (h:x) + (16 ? m) C C C C C C imm af ii 2 and # opr and opr and opr and opr ,x and opr ,x and ,x and opr ,sp and opr ,sp logical and a ? (a) & (m) 0 C C C imm dir ext ix2 ix1 ix sp1 sp2 a4 b4 c4 d4 e4 f4 9ee4 9ed4 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 9-cpu8_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . cpu MC68HC708XL36 50 cpu motorola asl opr asla aslx asl opr ,x asl ,x asl opr ,sp arithmetic shift left (same as lsl) CC dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 asr opr asra asrx asr opr ,x asr opr ,x asr opr ,sp arithmetic shift right CC dir inh inh ix1 ix sp1 37 47 57 67 77 9e67 dd ff ff 4 1 1 4 3 5 bcc rel branch if carry bit clear pc ? (pc) + 2 + rel ? (c) = 0 C C C C C C rel 24 rr 3 bclr n , opr clear bit n in m mn ? 0 CCCCCC dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 11 13 15 17 19 1b 1d 1f dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 bcs rel branch if carry bit set (same as blo) pc ? (pc) + 2 + rel ? (c) = 1 C C C C C C rel 25 rr 3 beq rel branch if equal pc ? (pc) + 2 + rel ? (z) = 1 C C C C C C rel 27 rr 3 bge opr branch if greater than or equal to (signed operands) pc ? (pc) + 2 + rel ? (n ? v ) = 0 C C C C C C rel 90 rr 3 bgt opr branch if greater than (signed operands) pc ? (pc) + 2 + rel ? (z) | (n ? v ) = 0 C C C C C C rel 92 rr 3 bhcc rel branch if half carry bit clear pc ? (pc) + 2 + rel ? (h) = 0 C C C C C C rel 28 rr 3 bhcs rel branch if half carry bit set pc ? (pc) + 2 + rel ? (h) = 1 C C C C C C rel 29 rr 3 bhi rel branch if higher pc ? (pc) + 2 + rel ? (c) | (z) = 0 C C C C C C rel 22 rr 3 bhs rel branch if higher or same (same as bcc) pc ? (pc) + 2 + rel ? (c) = 0 C C C C C C rel 24 rr 3 bih rel branch if irq pin high pc ? (pc) + 2 + rel ? irq = 1 C C C C C C rel 2f rr 3 bil rel branch if irq pin low pc ? (pc) + 2 + rel ? irq = 0 C C C C C C rel 2e rr 3 bit # opr bit opr bit opr bit opr ,x bit opr ,x bit ,x bit opr ,sp bit opr ,sp bit test (a) & (m) 0 C C C imm dir ext ix2 ix1 ix sp1 sp2 a5 b5 c5 d5 e5 f5 9ee5 9ed5 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ble opr branch if less than or equal to (signed operands) pc ? (pc) + 2 + rel ? (z) | (n ? v ) = 1 C C C C C C rel 93 rr 3 blo rel branch if lower (same as bcs) pc ? (pc) + 2 + rel ? (c) = 1 C C C C C C rel 25 rr 3 bls rel branch if lower or same pc ? (pc) + 2 + rel ? (c) | (z) = 1 C C C C C C rel 23 rr 3 blt opr branch if less than (signed operands) pc ? (pc) + 2 + rel ? (n ? v ) = 1 C C C C C C rel 91 rr 3 bmc rel branch if interrupt mask clear pc ? (pc) + 2 + rel ? (i) = 0 C C C C C C rel 2c rr 3 bmi rel branch if minus pc ? (pc) + 2 + rel ? (n) = 1 C C C C C C rel 2b rr 3 bms rel branch if interrupt mask set pc ? (pc) + 2 + rel ? (i) = 1 C C C C C C rel 2d rr 3 bne rel branch if not equal pc ? (pc) + 2 + rel ? (z) = 0 C C C C C C rel 26 rr 3 bpl rel branch if plus pc ? (pc) + 2 + rel ? (n) = 0 C C C C C C rel 2a rr 3 table 1. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 0 b0 b7 c 10-cpu8_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . cpu instruction set summary MC68HC708XL36 motorola cpu 51 bra rel branch always pc ? (pc) + 2 + rel C C C C C C rel 20 rr 3 brclr n , opr , rel branch if bit n in m clear pc ? (pc) + 3 + rel ? (mn) = 0 C C C C C dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 01 03 05 07 09 0b 0d 0f dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 brn rel branch never pc ? (pc) + 2 C C C C C C rel 21 rr 3 brset n , opr , rel branch if bit n in m set pc ? (pc) + 3 + rel ? (mn) = 1 C C C C C dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 00 02 04 06 08 0a 0c 0e dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr 5 5 5 5 5 5 5 5 bset n , opr set bit n in m mn ? 1 CCCCCC dir (b0) dir (b1) dir (b2) dir (b3) dir (b4) dir (b5) dir (b6) dir (b7) 10 12 14 16 18 1a 1c 1e dd dd dd dd dd dd dd dd 4 4 4 4 4 4 4 4 bsr rel branch to subroutine pc ? (pc) + 2; push (pcl) sp ? (sp) C 1; push (pch) sp ? (sp) C 1 pc ? (pc) + rel C C C C C C rel ad rr 4 cbeq opr,rel cbeqa # opr,rel cbeqx # opr,rel cbeq opr, x+ ,rel cbeq x+ ,rel cbeq opr, sp ,rel compare and branch if equal pc ? (pc) + 3 + rel ? (a) C (m) = $00 pc ? (pc) + 3 + rel ? (a) C (m) = $00 pc ? (pc) + 3 + rel ? (x) C (m) = $00 pc ? (pc) + 3 + rel ? (a) C (m) = $00 pc ? (pc) + 2 + rel ? (a) C (m) = $00 pc ? (pc) + 4 + rel ? (a) C (m) = $00 CCCCCC dir imm imm ix1+ ix+ sp1 31 41 51 61 71 9e61 dd rr ii rr ii rr ff rr rr ff rr 5 4 4 5 4 6 clc clear carry bit c ? 0 C C C C C 0 inh 98 1 cli clear interrupt mask i ? 0 C C 0 C C C inh 9a 2 clr opr clra clrx clrh clr opr ,x clr ,x clr opr ,sp clear m ? $00 a ? $00 x ? $00 h ? $00 m ? $00 m ? $00 m ? $00 0CC01C dir inh inh inh ix1 ix sp1 3f 4f 5f 8c 6f 7f 9e6f dd ff ff 3 1 1 1 3 2 4 cmp # opr cmp opr cmp opr cmp opr ,x cmp opr ,x cmp ,x cmp opr ,sp cmp opr ,sp compare a with m (a) C (m) CC imm dir ext ix2 ix1 ix sp1 sp2 a1 b1 c1 d1 e1 f1 9ee1 9ed1 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 com opr coma comx com opr ,x com ,x com opr ,sp complement (ones complement) m ? ( m) = $ff C (m) a ? ( a) = $ff C (m) x ? ( x) = $ff C (m) m ? ( m) = $ff C (m) m ? ( m) = $ff C (m) m ? ( m) = $ff C (m) 0CC 1 dir inh inh ix1 ix sp1 33 43 53 63 73 9e63 dd ff ff 4 1 1 4 3 5 table 1. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc 11-cpu8_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . cpu MC68HC708XL36 52 cpu motorola cphx # opr cphx opr compare h:x with m (h:x) C (m:m + 1) CC imm dir 65 75 ii ii+1 dd 3 4 cpx # opr cpx opr cpx opr cpx ,x cpx opr ,x cpx opr ,x cpx opr ,sp cpx opr ,sp compare x with m (x) C (m) CC imm dir ext ix2 ix1 ix sp1 sp2 a3 b3 c3 d3 e3 f3 9ee3 9ed3 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 daa decimal adjust a (a) 10 uCC inh 72 2 dbnz opr,rel dbnza rel dbnzx rel dbnz opr, x ,rel dbnz x ,rel dbnz opr, sp ,rel decrement and branch if not zero a ? (a) C 1 or m ? (m) C 1 or x ? (x) C 1 pc ? (pc) + 3 + rel ? (result) 1 0 pc ? (pc) + 2 + rel ? (result) 1 0 pc ? (pc) + 2 + rel ? (result) 1 0 pc ? (pc) + 3 + rel ? (result) 1 0 pc ? (pc) + 2 + rel ? (result) 1 0 pc ? (pc) + 4 + rel ? (result) 1 0 CCCCCC dir inh inh ix1 ix sp1 3b 4b 5b 6b 7b 9e6b dd rr rr rr ff rr rr ff rr 5 3 3 5 4 6 dec opr deca decx dec opr ,x dec ,x dec opr ,sp decrement m ? (m) C 1 a ? (a) C 1 x ? (x) C 1 m ? (m) C 1 m ? (m) C 1 m ? (m) C 1 CC C dir inh inh ix1 ix sp1 3a 4a 5a 6a 7a 9e6a dd ff ff 4 1 1 4 3 5 div divide a ? (h:a)/(x) h ? remainder CCCC inh 52 7 eor # opr eor opr eor opr eor opr ,x eor opr ,x eor ,x eor opr ,sp eor opr ,sp exclusive or m with a a ? (a ? m) 0 C C C imm dir ext ix2 ix1 ix sp1 sp2 a8 b8 c8 d8 e8 f8 9ee8 9ed8 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 inc opr inca incx inc opr ,x inc ,x inc opr ,sp increment m ? (m) + 1 a ? (a) + 1 x ? (x) + 1 m ? (m) + 1 m ? (m) + 1 m ? (m) + 1 CC C dir inh inh ix1 ix sp1 3c 4c 5c 6c 7c 9e6c dd ff ff 4 1 1 4 3 5 jmp opr jmp opr jmp opr ,x jmp opr ,x jmp ,x jump pc ? jump address C C C C C C dir ext ix2 ix1 ix bc cc dc ec fc dd hh ll ee ff ff 2 3 4 3 2 jsr opr jsr opr jsr opr ,x jsr opr ,x jsr ,x jump to subroutine pc ? (pc) + n ( n = 1, 2, or 3) push (pcl); sp ? (sp) C 1 push (pch); sp ? (sp) C 1 pc ? unconditional address CCCCCC dir ext ix2 ix1 ix bd cd dd ed fd dd hh ll ee ff ff 4 5 6 5 4 lda # opr lda opr lda opr lda opr ,x lda opr ,x lda ,x lda opr ,sp lda opr ,sp load a from m a ? (m) 0 C C C imm dir ext ix2 ix1 ix sp1 sp2 a6 b6 c6 d6 e6 f6 9ee6 9ed6 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 ldhx # opr ldhx opr load h:x from m h:x ? ( m:m + 1 ) 0CC C imm dir 45 55 ii jj dd 3 4 table 1. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc 12-cpu8_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . cpu instruction set summary MC68HC708XL36 motorola cpu 53 ldx # opr ldx opr ldx opr ldx opr ,x ldx opr ,x ldx ,x ldx opr ,sp ldx opr ,sp load x from m x ? (m) 0 C C C imm dir ext ix2 ix1 ix sp1 sp2 ae be ce de ee fe 9eee 9ede ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 lsl opr lsla lslx lsl opr ,x lsl ,x lsl opr ,sp logical shift left (same as asl) CC dir inh inh ix1 ix sp1 38 48 58 68 78 9e68 dd ff ff 4 1 1 4 3 5 lsr opr lsra lsr x lsr opr ,x lsr ,x lsr opr ,sp logical shift right CC0 dir inh inh ix1 ix sp1 34 44 54 64 74 9e64 dd ff ff 4 1 1 4 3 5 mov opr,opr mov opr, x+ mov # opr,opr mov x+ ,opr move (m) destination ? (m) source h:x ? (h:x) + 1 (ix+d, dix+) 0CC C dd dix+ imd ix+d 4e 5e 6e 7e dd dd dd ii dd dd 5 4 4 4 mul unsigned multiply x:a ? (x) (a) C 0 C C C 0 inh 42 5 neg opr nega negx neg opr ,x neg ,x neg opr ,sp negate (twos complement) m ? C(m) = $00 C (m) a ? C(a) = $00 C (a) x ? C(x) = $00 C (x) m ? C(m) = $00 C (m) m ? C(m) = $00 C (m) CC dir inh inh ix1 ix sp1 30 40 50 60 70 9e60 dd ff ff 4 1 1 4 3 5 nop no operation none C C C C C C inh 9d 1 nsa nibble swap a a ? (a[3:0]:a[7:4]) C C C C C C inh 62 3 ora # opr ora opr ora opr ora opr ,x ora opr ,x ora ,x ora opr ,sp ora opr ,sp inclusive or a and m a ? (a) | (m) 0 C C C imm dir ext ix2 ix1 ix sp1 sp2 aa ba ca da ea fa 9eea 9eda ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 psha push a onto stack push (a); sp ? (sp ) C 1 C C C C C C inh 87 2 pshh push h onto stack push (h) ; sp ? (sp ) C 1 CCCCCCinh 8b 2 pshx push x onto stack push (x) ; sp ? (sp ) C 1 CCCCCCinh 89 2 pula pull a from stack sp ? (sp + 1); pull ( a ) CCCCCCinh 86 2 pulh pull h from stack sp ? (sp + 1); pull ( h ) CCCCCCinh 8a 2 pulx pull x from stack sp ? (sp + 1); pull ( x ) CCCCCCinh 88 2 rol opr rola rolx rol opr ,x rol ,x rol opr ,sp rotate left through carry CC dir inh inh ix1 ix sp1 39 49 59 69 79 9e69 dd ff ff 4 1 1 4 3 5 table 1. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc c b0 b7 0 b0 b7 c 0 c b0 b7 13-cpu8_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . cpu MC68HC708XL36 54 cpu motorola ror opr rora rorx ror opr ,x ror ,x ror opr ,sp rotate right through carry CC dir inh inh ix1 ix sp1 36 46 56 66 76 9e66 dd ff ff 4 1 1 4 3 5 rsp reset stack pointer sp ? $ff C C C C C C inh 9c 1 rti return from interrupt sp ? (sp) + 1; pull (ccr) sp ? (sp) + 1; pull (a) sp ? (sp) + 1; pull (x) sp ? (sp) + 1; pull (pch) sp ? (sp) + 1; pull (pcl) inh 80 7 rts return from subroutine sp ? sp + 1 ; pull ( pch) sp ? sp + 1; pull (pcl) CCCCCCinh 81 4 sbc # opr sbc opr sbc opr sbc opr ,x sbc opr ,x sbc ,x sbc opr ,sp sbc opr ,sp subtract with carry a ? (a) C (m) C (c) CC imm dir ext ix2 ix1 ix sp1 sp2 a2 b2 c2 d2 e2 f2 9ee2 9ed2 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 sec set carry bit c ? 1 C C C C C 1 inh 99 1 sei set interrupt mask i ? 1 C C 1 C C C inh 9b 2 sta opr sta opr sta opr ,x sta opr ,x sta ,x sta opr ,sp sta opr ,sp store a in m m ? (a) 0 C C C dir ext ix2 ix1 ix sp1 sp2 b7 c7 d7 e7 f7 9ee7 9ed7 dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sthx opr store h:x in m (m:m + 1) ? (h:x) 0 C C C dir 35 dd 4 stop enable irq pin; stop oscillator i ? 0; stop oscillator C C 0 C C C inh 8e 1 stx opr stx opr stx opr ,x stx opr ,x stx ,x stx opr ,sp stx opr ,sp store x in m m ? (x) 0 C C C dir ext ix2 ix1 ix sp1 sp2 bf cf df ef ff 9eef 9edf dd hh ll ee ff ff ff ee ff 3 4 4 3 2 4 5 sub # opr sub opr sub opr sub opr ,x sub opr ,x sub ,x sub opr ,sp sub opr ,sp subtract a ? (a) C (m) CC imm dir ext ix2 ix1 ix sp1 sp2 a0 b0 c0 d0 e0 f0 9ee0 9ed0 ii dd hh ll ee ff ff ff ee ff 2 3 4 4 3 2 4 5 swi software interrupt pc ? (pc) + 1; push (pcl) sp ? (sp) C 1; push (pch) sp ? (sp) C 1; push (x) sp ? (sp) C 1; push (a) sp ? (sp) C 1; push (ccr) sp ? (sp) C 1; i ? 1 pch ? interrupt vector high byte pcl ? interrupt vector low byte CC1CCCinh 83 9 tap transfer a to ccr ccr ? (a) inh 84 2 tax transfer a to x x ? (a) C C C C C C inh 97 1 table 1. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc b0 b7 c 14-cpu8_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . cpu opcode map MC68HC708XL36 motorola cpu 55 opcode map table 2 on page 56 is the opcode map for the MC68HC708XL36. tpa transfer ccr to a a ? (ccr) C C C C C C inh 85 1 tst opr tsta tstx tst opr ,x tst ,x tst opr ,sp test for negative or zero (a) C $00 or (x) C $00 or (m) C $00 0 C C C dir inh inh ix1 ix sp1 3d 4d 5d 6d 7d 9e6d dd ff ff 3 1 1 3 2 4 tsx transfer sp to h:x h:x ? (sp) + 1 C C C C C C inh 95 2 txa transfer x to a a ? (x) C C C C C C inh 9f 1 txs transfer h:x to sp (sp) ? (h:x) C 1 C C C C C C inh 94 2 a accumulator n any bit c carry/borrow bit opr operand (one or two bytes) ccr condition code register pc program counter dd direct address of operand pch program counter high byte dd rr direct address of operand and relative offset of branch instruction pcl program counter low byte dd direct to direct addressing mode rel relative addressing mode dir direct addressing mode rel relative program counter offset byte dix+ direct to indexed with post increment addressing mode rr relative program counter offset byte ee ff high and low bytes of offset in indexed, 16-bit offset addressing sp1 stack pointer, 8-bit offset addressing mode ext extended addressing mode sp2 stack pointer 16-bit offset addressing mode ff offset byte in indexed, 8-bit offset addressing sp stack pointer h half-carry bit u unde?ned h index register high byte v over?ow bit hh ll high and low bytes of operand address in extended addressing x index register low byte i interrupt mask z zero bit ii immediate operand byte & logical and imd immediate source to direct destination addressing mode | logical or imm immediate addressing mode ? logical exclusive or inh inherent addressing mode ( ) contents of ix indexed, no offset addressing mode C( ) negation (twos complement) ix+ indexed, no offset, post increment addressing mode # immediate value ix+d indexed with post increment to direct addressing mode ? sign extend ix1 indexed, 8-bit offset addressing mode ? loaded with ix1+ indexed, 8-bit offset, post increment addressing mode ? if ix2 indexed, 16-bit offset addressing mode : concatenated with m memory location set or cleared n negative bit not affected table 1. instruction set summary (continued) source form operation description effect on ccr address mode opcode operand cycles vh i nzc 15-cpu8_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . cpu MC68HC708XL36 56 cpu motorola table 2. opcode map bit manipulation branch read-modify-write control register/memory dir dir rel dir inh inh ix1 sp1 ix inh inh imm dir ext ix2 sp2 ix1 sp1 ix 0 1234569e6789 abcd9ede9eef 0 5 brset0 3 dir 4 bset0 2 dir 3 bra 2 rel 4 neg 2 dir 1 nega 1 inh 1 negx 1 inh 4 neg 2 ix1 5 neg 3 sp1 3 neg 1ix 7 rti 1 inh 3 bge 2 rel 2 sub 2 imm 3 sub 2 dir 4 sub 3 ext 4 sub 3 ix2 5 sub 4 sp2 3 sub 2 ix1 4 sub 3 sp1 2 sub 1ix 1 5 brclr0 3 dir 4 bclr0 2 dir 3 brn 2 rel 5 cbeq 3 dir 4 cbeqa 3 imm 4 cbeqx 3 imm 5 cbeq 3 ix1+ 6 cbeq 4 sp1 4 cbeq 2 ix+ 4 rts 1 inh 3 blt 2 rel 2 cmp 2 imm 3 cmp 2 dir 4 cmp 3 ext 4 cmp 3 ix2 5 cmp 4 sp2 3 cmp 2 ix1 4 cmp 3 sp1 2 cmp 1ix 2 5 brset1 3 dir 4 bset1 2 dir 3 bhi 2 rel 5 mul 1 inh 7 div 1 inh 3 nsa 1 inh 2 daa 1 inh 3 bgt 2 rel 2 sbc 2 imm 3 sbc 2 dir 4 sbc 3 ext 4 sbc 3 ix2 5 sbc 4 sp2 3 sbc 2 ix1 4 sbc 3 sp1 2 sbc 1ix 3 5 brclr1 3 dir 4 bclr1 2 dir 3 bls 2 rel 4 com 2 dir 1 coma 1 inh 1 comx 1 inh 4 com 2 ix1 5 com 3 sp1 3 com 1ix 9 swi 1 inh 3 ble 2 rel 2 cpx 2 imm 3 cpx 2 dir 4 cpx 3 ext 4 cpx 3 ix2 5 cpx 4 sp2 3 cpx 2 ix1 4 cpx 3 sp1 2 cpx 1ix 4 5 brset2 3 dir 4 bset2 2 dir 3 bcc 2 rel 4 lsr 2 dir 1 lsra 1 inh 1 lsrx 1 inh 4 lsr 2 ix1 5 lsr 3 sp1 3 lsr 1ix 2 ta p 1 inh 2 txs 1 inh 2 and 2 imm 3 and 2 dir 4 and 3 ext 4 and 3 ix2 5 and 4 sp2 3 and 2 ix1 4 and 3 sp1 2 and 1ix 5 5 brclr2 3 dir 4 bclr2 2 dir 3 bcs 2 rel 4 sthx 2 dir 3 ldhx 3 imm 4 ldhx 2 dir 3 cphx 3 imm 4 cphx 2 dir 1 tpa 1 inh 2 tsx 1 inh 2 bit 2 imm 3 bit 2 dir 4 bit 3 ext 4 bit 3 ix2 5 bit 4 sp2 3 bit 2 ix1 4 bit 3 sp1 2 bit 1ix 6 5 brset3 3 dir 4 bset3 2 dir 3 bne 2 rel 4 ror 2 dir 1 rora 1 inh 1 rorx 1 inh 4 ror 2 ix1 5 ror 3 sp1 3 ror 1ix 2 pula 1 inh 2 lda 2 imm 3 lda 2 dir 4 lda 3 ext 4 lda 3 ix2 5 lda 4 sp2 3 lda 2 ix1 4 lda 3 sp1 2 lda 1ix 7 5 brclr3 3 dir 4 bclr3 2 dir 3 beq 2 rel 4 asr 2 dir 1 asra 1 inh 1 asrx 1 inh 4 asr 2 ix1 5 asr 3 sp1 3 asr 1ix 2 psha 1 inh 1 ta x 1 inh 2 ais 2 imm 3 sta 2 dir 4 sta 3 ext 4 sta 3 ix2 5 sta 4 sp2 3 sta 2 ix1 4 sta 3 sp1 2 sta 1ix 8 5 brset4 3 dir 4 bset4 2 dir 3 bhcc 2 rel 4 lsl 2 dir 1 lsla 1 inh 1 lslx 1 inh 4 lsl 2 ix1 5 lsl 3 sp1 3 lsl 1ix 2 pulx 1 inh 1 clc 1 inh 2 eor 2 imm 3 eor 2 dir 4 eor 3 ext 4 eor 3 ix2 5 eor 4 sp2 3 eor 2 ix1 4 eor 3 sp1 2 eor 1ix 9 5 brclr4 3 dir 4 bclr4 2 dir 3 bhcs 2 rel 4 rol 2 dir 1 rola 1 inh 1 rolx 1 inh 4 rol 2 ix1 5 rol 3 sp1 3 rol 1ix 2 pshx 1 inh 1 sec 1 inh 2 adc 2 imm 3 adc 2 dir 4 adc 3 ext 4 adc 3 ix2 5 adc 4 sp2 3 adc 2 ix1 4 adc 3 sp1 2 adc 1ix a 5 brset5 3 dir 4 bset5 2 dir 3 bpl 2 rel 4 dec 2 dir 1 deca 1 inh 1 decx 1 inh 4 dec 2 ix1 5 dec 3 sp1 3 dec 1ix 2 pulh 1 inh 2 cli 1 inh 2 ora 2 imm 3 ora 2 dir 4 ora 3 ext 4 ora 3 ix2 5 ora 4 sp2 3 ora 2 ix1 4 ora 3 sp1 2 ora 1ix b 5 brclr5 3 dir 4 bclr5 2 dir 3 bmi 2 rel 5 dbnz 3 dir 3 dbnza 2 inh 3 dbnzx 2 inh 5 dbnz 3 ix1 6 dbnz 4 sp1 4 dbnz 2ix 2 pshh 1 inh 2 sei 1 inh 2 add 2 imm 3 add 2 dir 4 add 3 ext 4 add 3 ix2 5 add 4 sp2 3 add 2 ix1 4 add 3 sp1 2 add 1ix c 5 brset6 3 dir 4 bset6 2 dir 3 bmc 2 rel 4 inc 2 dir 1 inca 1 inh 1 incx 1 inh 4 inc 2 ix1 5 inc 3 sp1 3 inc 1ix 1 clrh 1 inh 1 rsp 1 inh 2 jmp 2 dir 3 jmp 3 ext 4 jmp 3 ix2 3 jmp 2 ix1 2 jmp 1ix d 5 brclr6 3 dir 4 bclr6 2 dir 3 bms 2 rel 3 tst 2 dir 1 tsta 1 inh 1 tstx 1 inh 3 tst 2 ix1 4 tst 3 sp1 2 tst 1ix 1 nop 1 inh 4 bsr 2 rel 4 jsr 2 dir 5 jsr 3 ext 6 jsr 3 ix2 5 jsr 2 ix1 4 jsr 1ix e 5 brset7 3 dir 4 bset7 2 dir 3 bil 2 rel 5 mov 3dd 4 mov 2 dix+ 4 mov 3 imd 4 mov 2 ix+d 1 stop 1 inh * 2 ldx 2 imm 3 ldx 2 dir 4 ldx 3 ext 4 ldx 3 ix2 5 ldx 4 sp2 3 ldx 2 ix1 4 ldx 3 sp1 2 ldx 1ix f 5 brclr7 3 dir 4 bclr7 2 dir 3 bih 2 rel 3 clr 2 dir 1 clra 1 inh 1 clrx 1 inh 3 clr 2 ix1 4 clr 3 sp1 2 clr 1ix 1 wait 1 inh 1 txa 1 inh 2 aix 2 imm 3 stx 2 dir 4 stx 3 ext 4 stx 3 ix2 5 stx 4 sp2 3 stx 2 ix1 4 stx 3 sp1 2 stx 1ix inh inherent rel relative sp1 stack pointer, 8-bit offset imm immediate ix indexed, no offset sp2 stack pointer, 16-bit offset dir direct ix1 indexed, 8-bit offset ix+ indexed, no offset with ext extended ix2 indexed, 16-bit offset post increment dd direct-direct imd immediate-direct ix1+ indexed, 1-byte offset with ix+d indexed-direct dix+ direct-indexed post increment * pre-byte for stack pointer indexed instructions 0 high byte of opcode in hexadecimal low byte of opcode in hexadecimal 0 5 brset0 3 dir cycles opcode mnemonic number of bytes / addressing mode msb lsb msb lsb 16-cpu8_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC708XL36 motorola resets and interrupts 57 resets and interrupts resets and interrupts contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .58 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 cop reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 low-voltage inhibit reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 illegal opcode reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 illegal address reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 reset status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .61 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 effects . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .62 sources . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 swi instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 break interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 irq1 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 cgm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 dma . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .66 tim . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 spi . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .67 sci . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 irq2 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 kb0Ckb7 pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 interrupt status registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 interrupt status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 interrupt status register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 interrupt status register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 1-ri24_e f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets and interrupts MC68HC708XL36 58 resets and interrupts motorola introduction resets and interrupts are responses to exceptional events during program execution. a reset reinitializes the mcu to its startup condition. an interrupt vectors the program counter to a service routine. resets a reset returns the mcu to a known startup condition and begins program execution from a user-defined memory location. effects a reset: ? immediately stops the operation of the instruction being executed. ? initializes certain control and status bits. ? loads the program counter with a user-defined reset vector address from locations $fffe and $ffff. ? selects cgmxclk divided by four as the bus clock. external reset a logic 0 applied to the rst pin for a time, t irl , generates an external reset. an external reset sets the pin bit in the reset status register. internal reset sources: ? power-on reset ? cop ? low-voltage inhibit ? illegal opcode ? illegal address all internal reset sources pull the rst pin low for 32 cgmxclk cycles to allow resetting of external devices. the mcu is held in reset for an additional 32 cgmxclk cycles after releasing the rst pin. 2-ri24_e f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets and interrupts resets MC68HC708XL36 motorola resets and interrupts 59 figure 1. internal reset timing power-on reset a power-on reset (por) is an internal reset caused by a positive transition on the v dd pin. a power-on reset: ? holds the clocks to the cpu and modules inactive for an oscillator stabilization delay of 4096 cgmxclk cycles. ? drives the rst pin low during the oscillator stabilization delay. ? releases the rst pin 32 cgmxclk cycles after the oscillator stabilization delay. ? releases the cpu to begin the reset vector sequence 64 cgmxclk cycles after the oscillator stabilization delay. ? sets the por bit in the reset status register and clears all other bits in the register. figure 2. power-on reset recovery rst pin pulled low by mcu internal 32 cycles 32 cycles cgmxclk reset porrst (1) osc1 cgmxclk cgmout rst pin internal 4096 cycles 32 cycles 32 cycles 1. porrst is an internally generated power-on reset pulse. reset 3-ri24_e f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets and interrupts MC68HC708XL36 60 resets and interrupts motorola cop reset a cop reset is an internal reset caused by an overflow of the cop counter. a cop reset sets the cop bit in the reset status register. to clear the cop counter and prevent a cop reset, write any value to the cop control register at location $ffff. low-voltage inhibit reset a low-voltage inhibit (lvi) reset is an internal reset caused by a drop in the power supply voltage to the lvi tripf voltage. an lvi reset: ? holds the clocks to the cpu and modules inactive for an oscillator stabilization delay of 4096 cgmxclk cycles after the power supply voltage rises to the lvi tripr voltage. ? drives the rst pin low for as long as v dd is below the lvi tripr voltage and during the oscillator stabilization delay. ? releases the rst pin 32 cgmxclk cycles after the oscillator stabilization delay. ? releases the cpu to begin the reset vector sequence 64 cgmxclk cycles after the oscillator stabilization delay. ? sets the lvi bit in the reset status register. illegal opcode reset an illegal opcode reset is an internal reset caused by an opcode that is not in the instruction set. an illegal opcode reset sets the ilop bit in the reset status register. if the stop enable bit, stop, in the configuration register is logic 0, the stop instruction causes an illegal opcode reset. illegal address reset an illegal address reset is an internal reset caused by an opcode fetch from an unmapped address. an illegal address reset sets the ilad bit in the reset status register. a data fetch from an unmapped address does not generate a reset. 4-ri24_e f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets and interrupts resets MC68HC708XL36 motorola resets and interrupts 61 reset status register this read-only register contains six flags that show the source of the last reset. clear the reset status register by reading it. a power-on reset sets the por bit and clears all other bits in the register. note: a reset source that becomes active before recovery from a previous reset can prevent the previous reset from setting its reset status bit. por power-on reset bit 1 = last reset caused by power-on 0 = read of rsr pin external reset bit 1 = last reset caused by external reset pin ( rst) 0 = por or read of rsr cop computer operating properly reset bit 1 = last reset caused by timeout of cop counter 0 = por or read of rsr ilop illegal opcode reset bit 1 = last reset caused by an illegal opcode 0 = por or read of rsr ilad illegal address reset bit 1 = last reset caused by an opcode fetch from an illegal address 0 = por or read of rsr lvi low-voltage inhibit reset bit 1 = last reset caused by low power supply voltage 0 = por or read of rsr address: $fe01 bit 7 654321 bit 0 read: por pin cop ilop ilad 0 lvi 0 write: por: 10000000 = unimplemented figure 3. reset status register (rsr) 5-ri24_e f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets and interrupts MC68HC708XL36 62 resets and interrupts motorola interrupts an interrupt temporarily changes the sequence of program execution to respond to a particular event. an interrupt does not stop the operation of the instruction being executed, but begins when the current instruction completes its operation. effects an interrupt: ? saves the cpu registers on the stack. at the end of the interrupt, the rti instruction recovers the cpu registers from the stack so that normal processing can resume. figure 4. interrupt stacking order condition code register accumulator index register (low byte)* program counter (high byte) program counter (low byte) ? ? ? ? ? ? 1 2 3 4 5 5 4 3 2 1 stacking order *high byte of index register is not stacked. $00ff default address on reset unstacking order 6-ri24_e f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets and interrupts interrupts MC68HC708XL36 motorola resets and interrupts 63 ? sets the interrupt mask (i bit) to prevent additional interrupts. once an interrupt is latched, no other interrupt can take precedence, regardless of its priority. ? loads the program counter with a user-defined vector address. after every instruction, the cpu checks all pending interrupts if the i bit is not set. if more than one interrupt is pending when an instruction is done, the highest priority interrupt is serviced first. if an interrupt is pending upon exit from the interrupt service routine, the pending interrupt is serviced before the lda instruction is executed. figure 5 . interrupt recognition example the lda opcode is prefetched by both the int1 and int2 rti instructions. however, in the case of the int1 rti prefetch, this is a redundant operation. note: to maintain compatibility with the m6805 family, the h register is not pushed on the stack during interrupt entry. if the interrupt service routine modifies the h register or uses the indexed addressing mode, save the h register and then restore it prior to exiting the routine. cli lda int1 pulh rti int2 background #$ff pshh int1 interrupt service routine pulh rti pshh int2 interrupt service routine routine 7-ri24_e f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets and interrupts MC68HC708XL36 64 resets and interrupts motorola figure 6. interrupt processing no no no yes no no yes no yes yes i bit set? from reset break interrupt? i bit set? irq1 interrupt? cgm interrupt? swi instruction? rti instruction? fetch next instruction. unstack cpu registers. stack cpu registers. set i bit. load pc with interrupt vector. execute instruction. yes yes all other hardware interrupts on chip 8-ri24_e f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets and interrupts interrupts MC68HC708XL36 motorola resets and interrupts 65 sources the following sources can generate cpu interrupt requests: 1. the i bit in the condition code register is a global mask for all interrupt sources except the swi instruction. 2. 0 = highest priority table 1. interrupt sources source flag mask (1) int register flag priority (2) vector address swi instruction none none none 0 $fffc C $fffd irq1 pin irq1f imask1 if1 1 $fffa C $fffb cgm pllf pllie if2 2 $fff8C$fff9 dma channel 0 ifc0 iec0 if3 3 $fff6C$fff7 dma channel 1 ifc1 iec1 dma channel 2 ifc2 iec2 tim channel 0 ch0f ch0ie if4 4 $fff4C$fff5 tim channel 1 ch1f ch1ie if5 5 $fff2C$fff3 tim channel 2 ch2f ch2ie if6 6 $fff0C$fff1 tim channel 3 ch3f ch3ie if7 7 $ffeeC$ffef tim over?ow tof toie if8 8 $ffecC$ffed spi receiver full sprf sprie if9 9 $ffeaC$ffeb spi over?ow ovrf errie spi mode fault modf errie spi transmitter empty spte sptie if10 10 $ffe8C$ffe9 sci receiver overrun or orie if11 11 $ffe6C$ffe7 sci noise flag nf neie sci framing error fe feie sci parity error pe peie sci receiver full scrf scrie if12 12 $ffe4C$ffe5 sci input idle idle ilie sci transmitter empty scte sctie if13 13 $ffe2C$ffe3 sci transmission complete tc tcie irq2 pin irq2f imask2 if14 14 $ffe0C$ffe1 keyboard pin keyf imaskk if15 15 $ffdeC$ffdf 9-ri24_e f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets and interrupts MC68HC708XL36 66 resets and interrupts motorola swi instruction the software interrupt instruction (swi) causes a nonmaskable interrupt. note: a software interrupt pushes pc onto the stack. an swi does not push pc C 1, as a hardware interrupt does. break interrupt the break module causes the cpu to execute an swi instruction at a software-programmable break point. irq1 pin a logic 0 on the irq1 pin latches an external interrupt request. cgm the cgm can generate a cpu interrupt request every time the phase-locked loop circuit (pll) enters or leaves the locked state. when the lock bit changes state, the pll flag (pllf) is set. the pll interrupt enable bit (pllie) enables pllf cpu interrupt requests. lock is in the pll bandwidth control register. pllf is in the pll control register. dma the dma module can generate a cpu interrupt request when a channel x cpu interrupt flag (ifcx) becomes set. ? ifcx is set at the end of a dma block transfer. the channel x cpu interrupt enable bit, iecx, enables dma channel x cpu interrupt requests. ? ifcx is set at the end of a dma transfer loop. the channel x cpu interrupt enable bit, iecx, enables dma channel x cpu interrupt requests. the ifcx bit is the dma status and control register. the iecx bit is in dma control register 1. 10-ri24_e f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets and interrupts interrupts MC68HC708XL36 motorola resets and interrupts 67 tim tim cpu interrupt sources: ? tim overflow flag (tof) the tof bit is set when the tim counter value rolls over to $0000 after matching the value in the tim counter modulo registers. the tim overflow interrupt enable bit, toie, enables tim overflow cpu interrupt requests. tof and toie are in the tim status and control register. ? tim channel flags (ch3fCch0f) the chxf bit is set when an input capture or output compare occurs on channel x. the channel x interrupt enable bit, chxie, enables channel x tim cpu interrupt requests. chxf and chxie are in the tim channel x status and control register. spi spi cpu interrupt sources: ? spi receiver full bit (sprf) the sprf bit is set every time a byte transfers from the shift register to the receive data register. the spi receiver interrupt enable bit, sprie, enables sprf cpu interrupt requests. sprf is in the spi status and control register and sprie is in the spi control register. ? spi transmitter empty (spte) the spte bit is set every time a byte transfers from the transmit data register to the shift register. the spi transmit interrupt enable bit, sptie, enables spte cpu interrupt requests. spte is in the spi status and control register and sptie is in the spi control register. ? mode fault bit (modf) the modf bit is set in a slave spi if the ss pin goes high during a transmission with the mode fault enable bit (modfen) set. in a master spi, the modf bit is set if the ss pin goes low at any time with the modfen bit set. the error interrupt enable bit, errie, enables modf cpu interrupt requests. modf, modfen, and errie are in the spi status and control register. ? overflow bit (ovrf) the ovrf bit is set if software does not read the byte in the receive data register before the next full byte enters the shift register. the error interrupt enable bit, errie, enables ovrf cpu interrupt requests. ovrf and errie are in the spi status and control register. 11-ri24_e f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets and interrupts MC68HC708XL36 68 resets and interrupts motorola sci sci cpu interrupt sources: ? sci transmitter empty bit (scte) scte is set when the sci data register transfers a character to the transmit shift register. the sci transmit interrupt enable bit, sctie, enables transmitter cpu interrupt requests. scte is in sci status register 1. sctie is in sci control register 2. ? transmission complete bit (tc) tc is set when the transmit shift register and the sci data register are empty and no break or idle character has been generated. the transmission complete interrupt enable bit, tcie, enables transmitter cpu interrupt requests. tc is in sci status register 1. tcie is in sci control register 2. ? sci receiver full bit (scrf) scrf is set when the receive shift register transfers a character to the sci data register. the sci receive interrupt enable bit, scrie, enables receiver cpu interrupts. scrf is in sci status register 1. scrie is in sci control register 2. ? idle input bit (idle) idle is set when 10 or 11 consecutive logic 1s shift in from the rxd pin. the idle line interrupt enable bit, ilie, enables idle cpu interrupt requests. idle is in sci status register 1. ilie is in sci control register 2. ? receiver overrun bit (or) or is set when the receive shift register shifts in a new character before the previous character was read from the sci data register. the overrun interrupt enable bit, orie, enables or to generate sci error cpu interrupt requests. or is in sci status register 1. orie is in sci control register 3. ? noise flag (nf) nf is set when the sci detects noise on incoming data or break characters, including start, data, and stop bits. the noise error interrupt enable bit, neie, enables nf to generate sci error cpu interrupt requests. nf is in sci status register 1. neie is in sci control register 3. 12-ri24_e f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets and interrupts interrupts MC68HC708XL36 motorola resets and interrupts 69 ? framing error bit (fe) fe is set when a logic 0 occurs where the receiver expects a stop bit. the framing error interrupt enable bit, feie, enables fe to generate sci error cpu interrupt requests. fe is in sci status register 1. feie is in sci control register 3. ? parity error bit (pe) pe is set when the sci detects a parity error in incoming data. the parity error interrupt enable bit, peie, enables pe to generate sci error cpu interrupt requests. pe is in sci status register 1. peie is in sci control register 3. irq2 pin a logic 0 on the irq2 pin latches an external interrupt request. kb0C kb7 pins a logic 0 on a keyboard interrupt pin latches an external interrupt request. 13-ri24_e f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets and interrupts MC68HC708XL36 70 resets and interrupts motorola interrupt status registers the flags in the interrupt status registers identify maskable interrupt sources. table 2 summarizes the interrupt sources and the interrupt status register flags that they set. the interrupt status registers can be useful for debugging. table 2. interrupt source flags interrupt source interrupt status register flag reset swi instruction irq1 pin if1 cgm if2 dma if3 tim channel 0 if4 tim channel 1 if5 tim channel 2 if6 tim channel 3 if7 tim over?ow if8 spi receiver if9 spi transmitter if10 sci error if11 sci receiver if12 sci transmitter if13 irq2 pin if14 keyboard pin if15 14-ri24_e f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets and interrupts interrupts MC68HC708XL36 motorola resets and interrupts 71 interrupt status register 1 if6Cif1 interrupt flags 6C1 these flags indicate the presence of interrupt requests from the sources shown in table 2 . 1 = interrupt request present 0 = no interrupt request present bits 0C1 always read 0 interrupt status register 2 if14Cif7 interrupt flags 14C7 these flags indicate the presence of interrupt requests from the sources shown in table 2 . 1 = interrupt request present 0 = no interrupt request present address: $fe04 bit 7 654321 bit 0 read: if6 if5 if4 if3 if2 if1 0 0 write: rrrrrrrr reset: 00000000 r = reserved figure 7. interrupt status register 1 (int1) address: $fe05 bit 7 654321 bit 0 read: if14 if13 if12 if11 if10 if9 if8 if7 write: rrrrrrrr reset: 00000000 r = reserved figure 8. interrupt status register 2 (int2) 15-ri24_e f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . resets and interrupts MC68HC708XL36 72 resets and interrupts motorola interrupt status register 3 bits 7C1 always read 0 if15 interrupt flag 15 this flag indicates the presence of an interrupt request from the source shown in table 2 . 1 = interrupt request present 0 = no interrupt request present address: $fe06 bit 7 654321 bit 0 read: 0000000 if15 write: rrrrrrrr reset: 00000000 r = reserved figure 9. interrupt status register 3 (int3) 16-ri24_e f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC708XL36 motorola low-power modes 73 low-power modes low-power modes contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 central processor unit (cpu) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 clock generator module (cgm) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 break module (brk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 computer operating properly module (cop) . . . . . . . . . . . . . . . . . . .76 direct memory access module (dma) . . . . . . . . . . . . . . . . . . . . . . . .76 external interrupt module (irq) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 keyboard interrupt module (kb) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .77 low-voltage inhibit module (lvi) . . . . . . . . . . . . . . . . . . . . . . . . . . . .78 serial communications interface module (sci) . . . . . . . . . . . . . . . . .78 serial peripheral interface module (spi) . . . . . . . . . . . . . . . . . . . . . . .79 timer interface module (tim) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 exiting wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 exiting stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 1-lp24_e f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . low-power modes MC68HC708XL36 74 low-power modes motorola introduction the wait instruction puts the mcu in a low-power standby mode in which the cpu clock is disabled but the bus clock continues to run. the stop instruction disables both the cpu clock and the bus clock. central processor unit (cpu) wait mode the wait instruction: ? clears the interrupt mask (i bit) in the condition code register, enabling interrupts. after exit from wait mode by interrupt, the i bit remains clear. after exit by reset, the i bit is set. ? disables the cpu clock. stop mode the stop instruction: ? clears the interrupt mask (i bit) in the condition code register, enabling external interrupts. after exit from stop mode by external interrupt, the i bit remains clear. after exit by reset, the i bit is set. ? disables the cpu clock. after exiting stop mode, the cpu clock begins running after the oscillator stabilization delay. 2-lp24_e f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . low-power modes clock generator module (cgm) MC68HC708XL36 motorola low-power modes 75 clock generator module (cgm) wait mode the cgm remains active in wait mode. before entering wait mode, software can disengage and turn off the pll by clearing the bcs and pllon bits in the pll control register (pctl). less power-sensitive applications can disengage the pll without turning it off. applications that require the pll to wake the mcu from wait mode also can deselect the pll output without turning off the pll. stop mode the stop instruction disables the cgm and holds low all cgm outputs (cgmxclk, cgmout, and cgmint). if the stop instruction is executed with the vco clock, cgmvclk, divided by two driving cgmout, the pll automatically clears the bcs bit in the pll control register (pctl), thereby selecting the crystal clock, cgmxclk, divided by two as the source of cgmout. when the mcu recovers from stop, the crystal clock divided by two drives cgmout and bcs remains clear. break module (brk) wait mode if enabled, the break module is active in wait mode. a dma-generated address that matches the break address registers in wait mode sets the bsw in the break status register. the dma can also use the break status and control register as its destination address in order to write to the brka and brke bits during wait mode. a dma write to the break status and control register sets the bsw bit. stop mode the break module is inactive in stop mode. the stop instruction does not affect break module register states. 3-lp24_e f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . low-power modes MC68HC708XL36 76 low-power modes motorola computer operating properly module (cop) wait mode the cop remains active in wait mode. to prevent a cop reset during wait mode, periodically clear the cop counter in a cpu interrupt routine or a dma service routine. stop mode stop mode turns off the cgmxclk input to the cop and clears the cop prescaler. service the cop immediately before entering or after exiting stop mode to ensure a full cop timeout period after entering or exiting stop mode. the stop bit in the configuration register (config) enables the stop instruction. to prevent inadvertently turning off the cop with a stop instruction, disable the stop instruction by clearing the stop bit. direct memory access module (dma) wait mode if enabled by the dmawe bit in the dma status and control register, the dma remains active in wait mode. the dma can transfer data to and from peripherals while the mcu remains in wait mode. if the wait instruction occurs during a dma transfer while dmawe is set, the dma transfer continues to completion. if the dmawe bit is clear, a wait instruction suspends the current dma transfer. if the dma priority bit (dmap) is set, the suspended transfer resumes when the mcu exits wait mode. stop mode the dma is inactive during stop mode. a stop instruction suspends any dma transfer in progress. if an external interrupt brings the mcu out of stop mode and the dma priority bit (dmap) is set, the suspended dma transfer resumes. if a reset brings the mcu out of stop mode, the transfer is aborted. 4-lp24_e f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . low-power modes external interrupt module (irq) MC68HC708XL36 motorola low-power modes 77 entering stop mode when a dma channel is enabled may fail to clear the interrupt mask (i bit) in the condition code register. to make sure the i bit is cleared when entering stop mode: ? before executing the stop instruction, wait until any current dma transfer is complete. then disable dma transfers by clearing bits tec[2:0] in dma control register 1. or, ? execute the clear-interrupt-mask instruction (cli) before entering stop mode. external interrupt module (irq) wait mode the irq module remains active in wait mode. clearing the imask1 or imask2 bit in the irq status and control register enables irq1 or irq2 cpu interrupt requests to bring the mcu out of wait mode. stop mode the irq module remains active in stop mode. clearing the imask1 or imask2 bit in the irq status and control register enables irq1 or irq2 cpu interrupt requests to bring the mcu out of stop mode. keyboard interrupt module (kb) wait mode the keyboard module remains active in wait mode. clearing the imaskk bit in the keyboard status and control register enables keyboard interrupt requests to bring the mcu out of wait mode. stop mode the keyboard module remains active in stop mode. clearing the imaskk bit in the keyboard status and control register enables keyboard interrupt requests to bring the mcu out of stop mode. 5-lp24_e f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . low-power modes MC68HC708XL36 78 low-power modes motorola low-voltage inhibit module (lvi) wait mode if enabled, the lvi module remains active in wait mode. if enabled to generate resets, the lvi module can generate a reset and bring the mcu out of wait mode. stop mode if enabled, the lvi module remains active in stop mode. if enabled to generate resets, the lvi module can generate a reset and bring the mcu out of stop mode. serial communications interface module (sci) wait mode the sci module remains active in wait mode. any enabled cpu interrupt request from the sci module can bring the mcu out of wait mode. if sci module functions are not required during wait mode, reduce power consumption by disabling the module before executing the wait instruction. the dma can service the sci without exiting wait mode. stop mode the sci module is inactive in stop mode. the stop instruction does not affect sci register states. sci module operation resumes after the mcu exits stop mode. because the internal clock is inactive during stop mode, entering stop mode during an sci transmission or reception results in invalid data. 6-lp24_e f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . low-power modes serial peripheral interface module (spi) MC68HC708XL36 motorola low-power modes 79 serial peripheral interface module (spi) wait mode the spi module remains active in wait mode. any enabled cpu interrupt request from the spi module can bring the mcu out of wait mode. if spi module functions are not required during wait mode, reduce power consumption by disabling the spi module before executing the wait instruction. the dma can service the spi without exiting wait mode. stop mode the spi module is inactive in stop mode. the stop instruction does not affect spi register states. spi operation resumes after an external interrupt. if stop mode is exited by reset, any transfer in progress is aborted, and the spi is reset. timer interface module (tim) wait mode the tim remains active in wait mode. any enabled cpu interrupt request from the tim can bring the mcu out of wait mode. if tim functions are not required during wait mode, reduce power consumption by stopping the tim before executing the wait instruction. the dma can service the tim without exiting wait mode. stop mode the tim is inactive in stop mode. the stop instruction does not affect register states or the state of the tim counter. tim operation resumes when the mcu exits stop mode after an external interrupt. 7-lp24_e f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . low-power modes MC68HC708XL36 80 low-power modes motorola exiting wait mode the following events restart the cpu clock and load the program counter with the reset vector or with an interrupt vector: ? external reset a logic 0 on the rst pin resets the mcu and loads the program counter with the contents of locations $fffe and $ffff. ? external interrupt a high-to-low transition on an external interrupt pin loads the program counter with the contents of locations: C $fffa and $fffb ( irq1 pin) C $ffe0 and $ffe1 ( irq2 pin) ? break interrupt a break interrupt loads the program counter with the contents of $fffc and $fffd. ? computer operating properly module (cop) reset a timeout of the cop counter resets the mcu and loads the program counter with the contents of $fffe and $ffff. ? low-voltage inhibit module (lvi) reset a power supply voltage below the lvi tripf voltage resets the mcu and loads the program counter with the contents of locations $fffe and $ffff. ? clock generator module (cgm) interrupt a cpu interrupt request from the phase-locked loop (pll) loads the program counter with the contents of $fff8 and $fff9. ? direct memory access module (dma) interrupt a cpu interrupt request from the dma loads the program counter with the contents of $fff6 and $fff7. 8-lp24_e f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . low-power modes exiting wait mode MC68HC708XL36 motorola low-power modes 81 ? timer interface module (tim) interrupt a cpu interrupt request from the tim loads the program counter with the contents of: C $ffec and $ffed (tim overflow) C $ffee and $ffef (tim channel 3) C $fff0 and $fff1 (tim channel 2) C $fff2 and $fff3 (tim channel 1) C $fff4 and $fff5 (tim channel 0) ? serial peripheral interface module (spi) interrupt a cpu interrupt request from the spi loads the program counter with the contents of: C $ffe8 and $ffe9 (spi transmitter) C $ffea and $ffeb (spi receiver) ? serial communications interface module (sci) interrupt a cpu interrupt request from the sci loads the program counter with the contents of: C $ffe2 and $ffe3 (sci transmitter) C $ffe4 and $ffe5 (sci receiver) C $ffe6 and $ffe7 (sci receiver error) 9-lp24_e f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . low-power modes MC68HC708XL36 82 low-power modes motorola exiting stop mode the following events restart the system clocks and load the program counter with the reset vector or with an interrupt vector: ? external reset a logic 0 on the rst pin resets the mcu and loads the program counter with the contents of locations $fffe and $ffff. ? external interrupt a high-to-low transition on an external interrupt pin loads the program counter with the contents of locations: C $fffa and $fffb ( irq1 pin) C $ffe0 and $ffe1 ( irq2 pin) C $ffde and $ffdf (keyboard interrupt pins) ? low-voltage inhibit (lvi) reset a power supply voltage below the lvi tripf voltage resets the mcu and loads the program counter with the contents of locations $fffe and $ffff. ? break interrupt a break interrupt loads the program counter with the contents of locations $fffc and $fffd. upon exit from stop mode, the system clocks begin running after an oscillator stabilization delay. a 12-bit stop recovery counter inhibits the system clocks for 4096 cgmxclk cycles after the reset or external interrupt. the short stop recovery bit, ssrec, in the configuration register controls the oscillator stabilization delay during stop recovery. setting ssrec reduces stop recovery time from 4096 cgmxclk cycles to 32 cgmxclk cycles. note: use the full stop recovery time (ssrec = 0) in applications that use an external crystal. 10-lp24_e f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC708XL36 motorola cgm 83 clock generator module cgm contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .84 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .85 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 crystal oscillator circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 phase-locked loop circuit (pll) . . . . . . . . . . . . . . . . . . . . . . . . . .88 circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 acquisition and tracking modes . . . . . . . . . . . . . . . . . . . . . . . . .90 manual and automatic pll bandwidth modes . . . . . . . . . . . . . .90 programming the pll . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .92 special programming exceptions . . . . . . . . . . . . . . . . . . . . . . . .93 base clock selector circuit. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 cgm external connections. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 crystal amplifier input pin (osc1) . . . . . . . . . . . . . . . . . . . . . . . . .96 crystal amplifier output pin (osc2) . . . . . . . . . . . . . . . . . . . . . . . .96 external filter capacitor pin (cgmxfc) . . . . . . . . . . . . . . . . . . . .96 analog power pin (vdda) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 oscillator enable signal (simoscen) . . . . . . . . . . . . . . . . . . . . . .96 crystal output frequency signal (cgmxclk) . . . . . . . . . . . . . . . .97 cgm base clock output (cgmout) . . . . . . . . . . . . . . . . . . . . . . .97 cgm cpu interrupt (cgmint) . . . . . . . . . . . . . . . . . . . . . . . . . . . .97 cgm registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 pll control register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 pll bandwidth control register (pbwc) . . . . . . . . . . . . . . . . . . .100 pll programming register (ppg) . . . . . . . . . . . . . . . . . . . . . . . .102 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .104 1-cgm1m_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . cgm MC68HC708XL36 84 cgm motorola low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 cgm during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 acquisition/lock time specifications . . . . . . . . . . . . . . . . . . . . . . . .106 acquisition/lock time definitions . . . . . . . . . . . . . . . . . . . . . . . . .106 parametric influences on reaction time . . . . . . . . . . . . . . . . . . .108 choosing a filter capacitor. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 reaction time calculation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 introduction the cgm generates the crystal clock signal, cgmxclk, which operates at the frequency of the crystal. the cgm also generates the base clock signal, cgmout, from which the system clocks are derived. cgmout is based on either the crystal clock divided by two or the phase-locked loop (pll) clock, cgmvclk, divided by two. the pll is a frequency generator designed for use with 1-mhz to 16-mhz crystals or ceramic resonators. the pll can generate an 8-mhz bus frequency without using a 32-mhz crystal. 2-cgm1m_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . cgm features MC68HC708XL36 motorola cgm 85 features features of the cgm include the following: ? phase-locked loop with output frequency in integer multiples of the crystal reference ? programmable hardware voltage-controlled oscillator (vco) for low-jitter operation ? automatic bandwidth control mode for low-jitter operation ? automatic frequency lock detector ? cpu interrupt on entry or exit from locked condition 3-cgm1m_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . cgm MC68HC708XL36 86 cgm motorola functional description the cgm consists of three major submodules: ? crystal oscillator circuit the crystal oscillator circuit generates the constant crystal frequency clock, cgmxclk. ? phase-locked loop (pll) the pll generates the programmable vco frequency clock cgmvclk. ? base clock selector circuit this software-controlled circuit selects either cgmxclk divided by two or the vco clock, cgmvclk, divided by two as the base clock, cgmout. the system clocks are derived from cgmout. figure 1 shows the structure of the cgm. crystal oscillator circuit the crystal oscillator circuit consists of an inverting amplifier and an external crystal. the osc1 pin is the input to the amplifier and the osc2 pin is the output. the simoscen signal enables the crystal oscillator circuit. the cgmxclk signal is the output of the crystal oscillator circuit and runs at a rate equal to the crystal frequency. cgmxclk is then buffered to produce cgmrclk, the pll reference clock. cgmxclk can be used by other modules which require precise timing for operation. the duty cycle of cgmxclk is not guaranteed to be 50% and depends on external factors, including the crystal and related external components. an externally generated clock also can feed the osc1 pin of the crystal oscillator circuit. connect the external clock to the osc1 pin and let the osc2 pin float. 4-cgm1m_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . cgm functional description MC68HC708XL36 motorola cgm 87 figure 1. cgm block diagram bcs phase detector loop filter frequency divider voltage controlled oscillator bandwidth control lock detector clock cgmxclk cgmout cgmvdv cgmvclk simoscen crystal oscillator interrupt control cgmint cgmrdv pll analog ? ? 2 cgmrclk select circuit lock auto acq vrs[7:4] pllie pllf mul[7:4] cpu clock , monitor mode a b s user mode when s = 0, cgmout = b osc2 osc1 v dda cgmxfc v ss pc3 pin stop recovery counter , cop prescaler, reset counter, sci baud rate generator ? ? 2 bus clock 5-cgm1m_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . cgm MC68HC708XL36 88 cgm motorola phase-locked loop circuit (pll) the pll is a frequency generator that can operate in either acquisition mode or tracking mode, depending on the accuracy of the output frequency. the pll can change between acquisition and tracking modes either automatically or manually. circuits the pll consists of the following circuits: ? voltage-controlled oscillator (vco) ? modulo vco frequency divider ? phase detector ? loop filter ? lock detector register name bit 7 654321 bit 0 pll control register (pctl) read: pllie pllf pllon bcs 1111 write: reset: 00101111 pll bandwidth control register (pbwc) read: auto lock a cq xld 0000 write: reset: pll programming register (ppg) read: mul7 mul6 mul5 mul4 vrs7 vrs6 vrs5 vrs4 write: reset: 01100110 = unimplemented figure 2. i/o register summary table 1. i/o register address summary register: pctl pbwc ppg address: $001c $001d $001e 6-cgm1m_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . cgm functional description MC68HC708XL36 motorola cgm 89 the operating range of the vco is programmable for a wide range of frequencies and for maximum immunity to external noise, including supply and cgmxfc noise. the vco frequency is bound to a range from roughly one-half to twice the center-of-range frequency, f vrs . modulating the voltage on the cgmxfc pin changes the frequency within this range. by design, f vrs is equal to the nominal center-of-range frequency, f nom , (4.9152 mhz) times a linear factor l, or (l)f nom . cgmrclk is the pll reference clock, a buffered version of cgmxclk. cgmrclk runs at a frequency, f rclk , and is fed to the pll through a buffer. the buffer output is the final reference clock, cgmrdv, running at a frequency f rdv =f rclk . the vcos output clock, cgmvclk, running at a frequency f vclk , is fed back through a programmable modulo divider. the modulo divider reduces the vco clock by a factor, n. the dividers output is the vco feedback clock, cgmvdv, running at a frequency f vdv =f vclk /n. (see programming the pll on page 92 for more information.) the phase detector then compares the vco feedback clock, cgmvdv, with the final reference clock, cgmrdv. a correction pulse is generated based on the phase difference between the two signals. the loop filter then slightly alters the dc voltage on the external capacitor connected to cgmxfc based on the width and direction of the correction pulse. the filter can make fast or slow corrections depending on its mode, described in acquisition and tracking modes on page 90. the value of the external capacitor and the reference frequency determines the speed of the corrections and the stability of the pll. the lock detector compares the frequencies of the vco feedback clock, cgmvdv, and the final reference clock, cgmrdv. therefore, the speed of the lock detector is directly proportional to the final reference frequency f rdv . the circuit determines the mode of the pll and the lock condition based on this comparison. 7-cgm1m_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . cgm MC68HC708XL36 90 cgm motorola acquisition and tracking modes the pll filter is manually or automatically configurable into one of two operating modes: ? acquisition mode in acquisition mode, the filter can make large frequency corrections to the vco. this mode is used at pll startup or when the pll has suffered a severe noise hit and the vco frequency is far off the desired frequency. when in acquisition mode, the acq bit is clear in the pll bandwidth control register. (see pll bandwidth control register (pbwc) on page 100.) ? tracking mode in tracking mode, the filter makes only small corrections to the frequency of the vco. pll jitter is much lower in tracking mode, but the response to noise is also slower. the pll enters tracking mode when the vco frequency is nearly correct, such as when the pll is selected as the base clock source. (see base clock selector circuit on page 94.) the pll is automatically in tracking mode when not in acquisition mode or when the acq bit is set. manual and automatic pll bandwidth modes the pll can change the bandwidth or operational mode of the loop filter manually or automatically. in automatic bandwidth control mode (auto = 1), the lock detector automatically switches between acquisition and tracking modes. automatic bandwidth control mode also is used to determine when the vco clock, cgmvclk, is safe to use as the source for the base clock, cgmout. (see pll bandwidth control register (pbwc) on page 100.) if pll cpu interrupt requests are enabled, the software can wait for a pll cpu interrupt request and then check the lock bit. if cpu interrupts are disabled, software can poll the lock bit continuously (during pll startup, usually) or at periodic intervals. in either case, when the lock bit is set, the vco clock is safe to use as the source for the base clock. (see base clock selector circuit on page 94.) if the vco is selected as the source for the base clock and the lock bit is clear, the pll has suffered a severe noise hit and the software must take appropriate action, depending on the application. (see interrupts on page 104.) 8-cgm1m_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . cgm functional description MC68HC708XL36 motorola cgm 91 the following conditions apply when the pll is in automatic bandwidth control mode: ? the acq bit (see pll bandwidth control register (pbwc) on page 100) is a read-only indicator of the mode of the filter. (see acquisition and tracking modes on page 90.) ? the acq bit is set when the vco frequency is within a certain tolerance, d trk , and is cleared when the vco frequency is out of a certain tolerance, d unt . (see specifications on page 333.) ? the lock bit is a read-only indicator of the locked state of the pll. ? the lock bit is set when the vco frequency is within a certain tolerance, d lock , and is cleared when the vco frequency is out of a certain tolerance, d unl . (see specifications on page 333.) ? cpu interrupts can occur if enabled (pllie = 1) when the plls lock condition changes, toggling the lock bit. (see pll control register on page 98.) the pll also can operate in manual mode (auto = 0). manual mode is used by systems that do not require an indicator of the lock condition for proper operation. such systems typically operate well below f busmax and require fast startup. the following conditions apply when in manual mode: ? acq is a writable control bit that controls the mode of the filter. before turning on the pll in manual mode, the acq bit must be clear. ? before entering tracking mode ( acq = 1), software must wait a given time, t acq (see specifications on page 333), after turning on the pll by setting pllon in the pll control register (pctl). ? software must wait a given time, t al , after entering tracking mode before selecting the pll as the clock source to cgmout (bcs = 1). ? the lock bit is disabled. ? cpu interrupts from the cgm are disabled. 9-cgm1m_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . cgm MC68HC708XL36 92 cgm motorola programming the pll use the following procedure to program the pll. 1. choose the desired bus frequency, f busdes . example: f busdes = 8 mhz 2. calculate the desired vco frequency, f vclkdes . f vclkdes = 4 f busdes example: f vclkdes = 4 8 mhz = 32 mhz 3. using a reference frequency, f rclk , equal to the crystal frequency, calculate the vco frequency multiplier, n. note: the round function means that the result is rounded to the nearest integer. example: 4. calculate the vco frequency, f vclk . example: f vclk = 8 4 mhz = 32 mhz 5. calculate the bus frequency, f bus , and compare f bus with f busdes . example: if the calculated f bus is not within the tolerance limits of your application, select another f busdes or another f rclk . n round f vclkdes f rclk ---------------- ? ?? = n 32 mhz 4 mhz -------------------- =8 = f vclk nf rclk = f bus f vclk 4 --------- = f bus 32 mhz 4 -------------------- = 8 mhz = 10-cgm1m_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . cgm functional description MC68HC708XL36 motorola cgm 93 6. using the value 4.9152 mhz for f nom , calculate the vco linear range multiplier, l. the linear range multiplier controls the frequency range of the pll. example: 7. calculate the vco center-of-range frequency, f vrs . the center-of-range frequency is the midpoint between the minimum and maximum frequencies attainable by the pll. f vrs = l f nom example: f vrs = 7 4.9152 mhz = 34.4 mhz note: for proper operation, exceeding the recommended maximum bus frequency or vco frequency can crash the mcu. 8. program the pll registers accordingly: a. in the upper four bits of the pll programming register (ppg), program the binary equivalent of n. b. in the lower four bits of the pll programming register (ppg), program the binary equivalent of l. special programming exceptions the programming method described in programming the pll on page 92 does not account for two possible exceptions. a value of 0 for n or l is meaningless when used in the equations given. to account for these exceptions: ? a 0 value for n is interpreted the same as a value of 1. ? a 0 value for l disables the pll and prevents its selection as the source for the base clock. (see base clock selector circuit on page 94.) l round f vclk f nom ---------- ? ?? = l 32 mhz 4.9152 mhz ------------------------------- - = 7 = f vrs f vclk C f nom 2 ------------- - 11-cgm1m_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . cgm MC68HC708XL36 94 cgm motorola base clock selector circuit this circuit is used to select either the crystal clock, cgmxclk, or the vco clock, cgmvclk, as the source of the base clock, cgmout. the two input clocks go through a transition control circuit that waits up to three cgmxclk cycles and three cgmvclk cycles to change from one clock source to the other. during this time, cgmout is held in stasis. the output of the transition control circuit is then divided by two to correct the duty cycle. therefore, the bus clock frequency, which is one-half of the base clock frequency, is one-fourth the frequency of the selected clock (cgmxclk or cgmvclk). the bcs bit in the pll control register (pctl) selects which clock drives cgmout. the vco clock cannot be selected as the base clock source if the pll is not turned on. the pll cannot be turned off if the vco clock is selected. the pll cannot be turned on or off simultaneously with the selection or deselection of the vco clock. the vco clock also cannot be selected as the base clock source if the factor l is programmed to a 0. this value would set up a condition inconsistent with the operation of the pll, so that the pll would be disabled and the crystal clock would be forced as the source of the base clock. cgm external connections in its typical configuration, the cgm requires seven external components. five of these are for the crystal oscillator and two are for the pll. the crystal oscillator is normally connected in a pierce oscillator configuration, as shown in figure 3 . figure 3 shows only the logical representation of the internal components and may not represent actual circuitry. the oscillator configuration uses five components: ? crystal, x 1 ? fixed capacitor, c 1 ? tuning capacitor, c 2 (can also be a fixed capacitor) ? feedback resistor, r b ? series resistor, r s (optional) 12-cgm1m_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . cgm functional description MC68HC708XL36 motorola cgm 95 the series resistor (r s ) may not be required for all ranges of operation, especially with high frequency crystals. refer to the crystal manufacturers data for more information. figure 3 also shows the external components for the pll: ? bypass capacitor, c byp ? filter capacitor, c f routing should be done with great care to minimize signal cross talk and noise. (see acquisition/lock time specifications on page 106 for routing information and more information on the filter capacitors value and its effects on pll performance.) figure 3. cgm external connections c 1 c 2 c f simoscen cgmxclk r b x 1 r s * c byp *r s can be 0 (shorted) when used with higher-frequency crystals. refer to manufacturers data. osc1 osc2 v ss cgmxfc v d d v dda 13-cgm1m_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . cgm MC68HC708XL36 96 cgm motorola i/o signals the following paragraphs describe the cgm i/o signals. crystal amplifier input pin (osc1) the osc1 pin is an input to the crystal oscillator amplifier. crystal amplifier output pin (osc2) the osc2 pin is the output of the crystal oscillator inverting amplifier. external filter capacitor pin (cgmxfc) the cgmxfc pin is required by the loop filter to filter out phase corrections. a small external capacitor is connected to this pin. note: to prevent noise problems, c f should be placed as close to the cgmxfc pin as possible, with minimum routing distances and no routing of other signals across the c f connection. analog power pin (v dda ) v dda is a power pin used by the analog portions of the pll. connect the v dda pin to the same voltage potential as the v dd pin. note: route v dda carefully for maximum noise immunity and place bypass capacitors as close as possible to the package. oscillator enable signal (simoscen) the simoscen signal enables the oscillator and pll. 14-cgm1m_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . cgm i/o signals MC68HC708XL36 motorola cgm 97 crystal output frequency signal (cgmxclk) cgmxclk is the crystal oscillator output signal. it runs at the full speed of the crystal (f xclk ) and comes directly from the crystal oscillator circuit. figure 3 shows only the logical relation of cgmxclk to osc1 and osc2 and may not represent the actual circuitry. the duty cycle of cgmxclk is unknown and may depend on the crystal and other external factors. also, the frequency and amplitude of cgmxclk can be unstable at startup. cgm base clock output (cgmout) cgmout is the clock output of the cgm. this signal is used to generate the mcu clocks. cgmout is a 50% duty cycle clock running at twice the bus frequency. cgmout is software programmable to be either the oscillator output, cgmxclk, divided by two or the vco clock, cgmvclk, divided by two. cgm cpu interrupt (cgmint) cgmint is the cpu interrupt signal generated by the pll lock detector. 15-cgm1m_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . cgm MC68HC708XL36 98 cgm motorola cgm registers the following registers control and monitor operation of the cgm: ? pll control register (pctl) (see pll control register on page 98.) ? pll bandwidth control register (pbwc) (see pll bandwidth control register (pbwc) on page 100.) ? pll programming register (ppg) (see pll programming register (ppg) on page 102.) pll control register the pll control register contains the interrupt enable and flag bits, the on/off switch, and the base clock selector bit. pllie pll interrupt enable bit this read/write bit enables the pll to generate a cpu interrupt request when the lock bit toggles, setting the pll flag, pllf. when the auto bit in the pll bandwidth control register (pbwc) is clear, pllie cannot be written and reads as logic 0. reset clears the pllie bit. 1 = pll cpu interrupt requests enabled 0 = pll cpu interrupt requests disabled pllf pll flag bit this read-only bit is set whenever the lock bit toggles. pllf generates a cpu interrupt request if the pllie bit also is set. pllf always reads as logic 0 when the auto bit in the pll bandwidth control register (pbwc) is clear. clear the pllf bit by reading the pll control register. reset clears the pllf bit. 1 = change in lock condition 0 = no change in lock condition address: $001c bit 7 654321 bit 0 read: pllie pllf pllon bcs 1111 write: reset: 00101111 = unimplemented figure 4. pll control register (pctl) 16-cgm1m_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . cgm cgm registers MC68HC708XL36 motorola cgm 99 note: do not inadvertently clear the pllf bit. any read or read-modify-write operation on the pll control register clears the pllf bit. pllon pll on bit this read/write bit activates the pll and enables the vco clock, cgmvclk. pllon cannot be cleared if the vco clock is driving the base clock, cgmout (bcs = 1). (see base clock selector circuit on page 94.) reset sets this bit so that the loop can stabilize as the mcu is powering up. 1 = pll on 0 = pll off bcs base clock select bit this read/write bit selects either the crystal oscillator output, cgmxclk, or the vco clock, cgmvclk, as the source of the cgm output, cgmout. cgmout frequency is one-half the frequency of the selected clock. bcs cannot be set while the pllon bit is clear. after toggling bcs, it may take up to three cgmxclk and three cgmvclk cycles to complete the transition from one source clock to the other. during the transition, cgmout is held in stasis. (see base clock selector circuit on page 94.) reset and the stop instruction clear the bcs bit. 1 = cgmvclk divided by two drives cgmout 0 = cgmxclk divided by two drives cgmout note: pllon and bcs have built-in protection that prevents the base clock selector circuit from selecting the vco clock as the source of the base clock if the pll is off. therefore, pllon cannot be cleared when bcs is set, and bcs cannot be set when pllon is clear. if the pll is off (pllon = 0), selecting cgmvclk requires two writes to the pll control register. (see base clock selector circuit on page 94.) pctl[3:0] unimplemented bits these bits provide no function and always read as logic 1s. 17-cgm1m_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . cgm MC68HC708XL36 100 cgm motorola pll bandwidth control register (pbwc) the pll bandwidth control register does the following: ? selects automatic or manual (software-controlled) bandwidth control mode ? indicates when the pll is locked ? in automatic bandwidth control mode, indicates when the pll is in acquisition or tracking mode ? in manual operation, forces the pll into acquisition or tracking mode auto automatic bandwidth control bit this read/write bit selects automatic or manual bandwidth control. when initializing the pll for manual operation (auto = 0), clear the acq bit before turning on the pll. reset clears the auto bit. 1 = automatic bandwidth control 0 = manual bandwidth control lock lock indicator bit when the auto bit is set, lock is a read-only bit that becomes set when the vco clock, cgmvclk, is locked (running at the programmed frequency). when the auto bit is clear, lock reads as logic 0 and has no meaning. reset clears the lock bit. 1 = vco frequency correct or locked 0 = vco frequency incorrect or unlocked address: $001d bit 7 654321 bit 0 read: auto lock a cq xld 0000 write: reset: 00000000 = unimplemented figure 5. pll bandwidth control register (pbwc) 18-cgm1m_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . cgm cgm registers MC68HC708XL36 motorola cgm 101 acq acquisition mode bit when the auto bit is set, acq is a read-only bit that indicates whether the pll is in acquisition mode or tracking mode. when the auto bit is clear, acq is a read/write bit that controls whether the pll is in acquisition or tracking mode. in automatic bandwidth control mode (auto = 1), the last-written value from manual operation is stored in a temporary location and is recovered when manual operation resumes. reset clears this bit, enabling acquisition mode. 1 = tracking mode 0 = acquisition mode xld crystal loss detect bit when the vco output, cgmvclk, is driving cgmout, this read/write bit can indicate whether the crystal reference frequency is active or not. 1 = crystal reference not active 0 = crystal reference active to check the status of the crystal reference, do the following: 1. write a logic 1 to xld. 2. wait n 4 cycles. (n is the vco frequency multiplier.) 3. read xld. the crystal loss detect function works only when the bcs bit is set, selecting cgmvclk to drive cgmout. when bcs is clear, xld always reads as logic 0. pbwc[3:0] reserved for test these bits enable test functions not available in user mode. to ensure software portability from development systems to user applications, software should write 0s to pbwc[3:0] whenever writing to pbwc. 19-cgm1m_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . cgm MC68HC708XL36 102 cgm motorola pll programming register (ppg) the pll programming register contains the programming information for the modulo feedback divider and the programming information for the hardware configuration of the vco. mul[7:4] multiplier select bits these read/write bits control the modulo feedback divider that selects the vco frequency multiplier, n. (see circuits on page 88 and programming the pll on page 92.) a value of $0 in the multiplier select bits configures the modulo feedback divider the same as a value of $1. reset initializes these bits to $6 to give a default multiply value of 6. address: $001e bit 7 654321 bit 0 read: mul7 mul6 mul5 mul4 vrs7 vrs6 vrs5 vrs4 write: reset: 01100110 figure 6. pll programming register (ppg) table 2. vco frequency multiplier (n) selection mul7:mul6:mul5:mul4 vco frequency multiplier (n) 0000 1 0001 1 0010 2 0011 3 1101 13 1110 14 1111 15 20-cgm1m_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . cgm cgm registers MC68HC708XL36 motorola cgm 103 note: the multiplier select bits have built-in protection that prevents them from being written when the pll is on (pllon = 1). vrs[7:4] vco range select bits these read/write bits control the hardware center-of-range linear multiplier l, which controls the hardware center-of-range frequency f vrs . (see circuits on page 88, programming the pll on page 92, and pll control register on page 98.) vrs[7:4] cannot be written when the pllon bit in the pll control register (pctl) is set. (see special programming exceptions on page 93.) a value of $0 in the vco range select bits disables the pll and clears the bcs bit in the pctl. (see base clock selector circuit on page 94 and special programming exceptions on page 93 for more information.) reset initializes the bits to $6 to give a default range multiply value of 6. note: the vco range select bits have built-in protection that prevents them from being written when the pll is on (pllon = 1) and prevents selection of the vco clock as the source of the base clock (bcs = 1) if the vco range select bits are all clear. the vco range select bits must be programmed correctly. incorrect programming can result in failure of the pll to achieve lock. 21-cgm1m_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . cgm MC68HC708XL36 104 cgm motorola interrupts when the auto bit is set in the pll bandwidth control register (pbwc), the pll can generate a cpu interrupt request every time the lock bit changes state. the pllie bit in the pll control register (pctl) enables cpu interrupt requests from the pll. pllf, the interrupt flag in the pctl, becomes set whether cpu interrupt requests are enabled or not. when the auto bit is clear, cpu interrupt requests from the pll are disabled and pllf reads as logic 0. software should read the lock bit after a pll cpu interrupt request to see if the request was due to an entry into lock or an exit from lock. when the pll enters lock, the vco clock, cgmvclk, divided by two can be selected as the cgmout source by setting bcs in the pctl. when the pll exits lock, the vco clock frequency is corrupt, and appropriate precautions should be taken. if the application is not frequency-sensitive, cpu interrupt requests should be disabled to prevent pll interrupt service routines from impeding software performance or from exceeding stack limitations. note: software can select the cgmvclk divided by two as the cgmout source even if the pll is not locked (lock = 0). therefore, software should make sure the pll is locked before setting the bcs bit. 22-cgm1m_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . cgm low-power modes MC68HC708XL36 motorola cgm 105 low-power modes the wait and stop instructions put the mcu in low-power-consump- tion standby modes. wait mode the cgm remains active in wait mode. before entering wait mode, software can disengage and turn off the pll by clearing the bcs and pllon bits in the pll control register (pctl). less power-sensitive applications can disengage the pll without turning it off. applications that require the pll to wake the mcu from wait mode also can deselect the pll output without turning off the pll. stop mode the stop instruction disables the cgm and holds low all cgm outputs (cgmxclk, cgmout, and cgmint). if the stop instruction is executed with the vco clock, cgmvclk, divided by two driving cgmout, the pll automatically clears the bcs bit in the pll control register (pctl), thereby selecting the crystal clock, cgmxclk, divided by two as the source of cgmout. when the mcu recovers from stop, the crystal clock divided by two drives cgmout and bcs remains clear. 23-cgm1m_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . cgm MC68HC708XL36 106 cgm motorola cgm during break interrupts the bcfe bit in the break flag control register (bfcr) enables software to clear status bits during the break state. (see break module on page 149.) to allow software to clear status bits during a break interrupt, write a logic 1 to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect the pllf bit during the break state, write a logic 0 to the bcfe bit. with bcfe at logic 0 (its default state), software can read and write the pll control register during the break state without affecting the pllf bit. acquisition/lock time specifications the acquisition and lock times of the pll are, in many applications, the most critical pll design parameters. proper design and use of the pll ensures the highest stability and lowest acquisition/lock times. acquisition/lock time definitions typical control systems refer to the acquisition time or lock time as the reaction time, within specified tolerances, of the system to a step input. in a pll, the step input occurs when the pll is turned on or when it suffers a noise hit. the tolerance is usually specified as a percent of the step input or when the output settles to the desired value plus or minus a percent of the frequency change. therefore, the reaction time is constant in this definition, regardless of the size of the step input. for example, consider a system with a 5% acquisition time tolerance. if a command instructs the system to change from 0 hz to 1 mhz, the acquisition time is the time taken for the frequency to reach 1 mhz 50 khz. fifty khz = 5% of the 1-mhz step input. if the system is operating at 1 mhz and suffers a C100 khz noise hit, the acquisition time is the time taken to return from 900 khz to 1 mhz 5 khz. five khz = 5% of the 100-khz step input. 24-cgm1m_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . cgm acquisition/lock time specifications MC68HC708XL36 motorola cgm 107 other systems refer to acquisition and lock times as the time the system takes to reduce the error between the actual output and the desired output to within specified tolerances. therefore, the acquisition or lock time varies according to the original error in the output. minor errors may not even be registered. typical pll applications prefer to use this definition because the system requires the output frequency to be within a certain tolerance of the desired frequency regardless of the size of the initial error. the discrepancy in these definitions makes it difficult to specify an acquisition or lock time for a typical pll. therefore, the definitions for acquisition and lock times for this module are as follows: ? acquisition time, t acq , is the time the pll takes to reduce the error between the actual output frequency and the desired output frequency to less than the tracking mode entry tolerance, d trk . acquisition time is based on an initial frequency error, (f des Cf orig )/f des , of not more than 100%. in automatic bandwidth control mode (see manual and automatic pll bandwidth modes on page 90), acquisition time expires when the acq bit becomes set in the pll bandwidth control register (pbwc). ? lock time, t lock , is the time the pll takes to reduce the error between the actual output frequency and the desired output frequency to less than the lock mode entry tolerance, d lock . lock time is based on an initial frequency error, (f des C f orig )/f des , of not more than 100%. in automatic bandwidth control mode, lock time expires when the lock bit becomes set in the pll bandwidth control register (pbwc). (see manual and automatic pll bandwidth modes on page 90.) obviously, the acquisition and lock times can vary according to how large the frequency error is and may be shorter or longer in many cases. 25-cgm1m_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . cgm MC68HC708XL36 108 cgm motorola parametric influences on reaction time acquisition and lock times are designed to be as short as possible while still providing the highest possible stability. these reaction times are not constant, however. many factors directly and indirectly affect the acquisition time. the most critical parameter which affects the reaction times of the pll is the reference frequency, f rdv . this frequency is the input to the phase detector and controls how often the pll makes corrections. for stability, the corrections must be small compared to the desired frequency, so several corrections are required to reduce the frequency error. therefore, the slower the reference the longer it takes to make these corrections. this parameter is also under user control via the choice of crystal frequency f xclk . another critical parameter is the external filter capacitor. the pll modifies the voltage on the vco by adding or subtracting charge from this capacitor. therefore, the rate at which the voltage changes for a given frequency error (thus change in charge) is proportional to the capacitor size. the size of the capacitor also is related to the stability of the pll. if the capacitor is too small, the pll cannot make small enough adjustments to the voltage and the system cannot lock. if the capacitor is too large, the pll may not be able to adjust the voltage in a reasonable time. (see choosing a filter capacitor on page 109.) also important is the operating voltage potential applied to v dda . the power supply potential alters the characteristics of the pll. a fixed value is best. variable supplies, such as batteries, are acceptable if they vary within a known range at very slow speeds. noise on the power supply is not acceptable, because it causes small frequency errors which continually change the acquisition time of the pll. temperature and processing also can affect acquisition time because the electrical characteristics of the pll change. the part operates as specified as long as these influences stay within the specified limits. external factors, however, can cause drastic changes in the operation of the pll. these factors include noise injected into the pll through the filter capacitor, filter capacitor leakage, stray impedances on the circuit board, and even humidity or circuit board contamination. 26-cgm1m_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . cgm acquisition/lock time specifications MC68HC708XL36 motorola cgm 109 choosing a filter capacitor as described in parametric influences on reaction time on page 108, the external filter capacitor, c f , is critical to the stability and reaction time of the pll. the pll is also dependent on reference frequency and supply voltage. the value of the capacitor must, therefore, be chosen with supply potential and reference frequency in mind. for proper operation, the external filter capacitor must be chosen according to the following equation: for acceptable values of c fact , (see specifications on page 333). for the value of v dda , choose the voltage potential at which the mcu is operating. if the power supply is variable, choose a value near the middle of the range of possible supply values. this equation does not always yield a commonly available capacitor size, so round to the nearest available size. if the value is between two different sizes, choose the higher value for better stability. choosing the lower size may seem attractive for acquisition time improvement, but the pll may become unstable. also, always choose a capacitor with a tight tolerance ( 20% or better) and low dissipation. reaction time calculation the actual acquisition and lock times can be calculated using the equations below. these equations yield nominal values under the following conditions: ? correct selection of filter capacitor, c f (see choosing a filter capacitor on page 109.) ? room temperature operation ? negligible external leakage on cgmxfc ? negligible noise the k factor in the equations is derived from internal pll parameters. k acq is the k factor when the pll is configured in acquisition mode, and c f c fact v dda f rdv ------------ - ? ?? = 27-cgm1m_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . cgm MC68HC708XL36 110 cgm motorola k trk is the k factor when the pll is configured in tracking mode. (see acquisition and tracking modes on page 90.) note the inverse proportionality between the lock time and the reference frequency. in automatic bandwidth control mode, the acquisition and lock times are quantized into units based on the reference frequency. (see manual and automatic pll bandwidth modes on page 90.) a certain number of clock cycles, n acq , is required to ascertain that the pll is within the tracking mode entry tolerance, d trk , before exiting acquisition mode. a certain number of clock cycles, n trk , is required to ascertain that the pll is within the lock mode entry tolerance, d lock . therefore, the acquisition time, t acq , is an integer multiple of n acq /f rdv , and the acquisition to lock time, t al , is an integer multiple of n trk /f rdv . also, since the average frequency over the entire measurement period must be within the specified tolerance, the total time usually is longer than t lock as calculated above. in manual mode, it is usually necessary to wait considerably longer than t lock before selecting the pll clock (see base clock selector circuit on page 94) because the factors described in parametric influences on reaction time on page 108 may slow the lock time considerably. t acq v dda f rdv ----------- - ? ?? 8 k acq ---------- ? ?? = t al v dda f rdv ----------- - ? ?? 4 k trk -------- ? ?? = t lock t acq t al + = 28-cgm1m_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC708XL36 motorola dma 111 direct memory access module dma contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .112 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .113 dma/cpu timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .117 hardware-initiated dma service requests. . . . . . . . . . . . . . . . . .121 software-initiated dma service requests . . . . . . . . . . . . . . . . . .122 dma latency. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 dma source/destination address calculation . . . . . . . . . . . . . . .123 low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130 stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .130 dma during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .131 dma registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .132 dma control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 dma status and control register . . . . . . . . . . . . . . . . . . . . . . . . .136 dma control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .139 dma channel control registers . . . . . . . . . . . . . . . . . . . . . . . . . .140 dma source address registers . . . . . . . . . . . . . . . . . . . . . . . . . .143 dma destination address registers. . . . . . . . . . . . . . . . . . . . . . .145 dma block length registers . . . . . . . . . . . . . . . . . . . . . . . . . . . .146 dma byte count registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .148 1-dma_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dma MC68HC708XL36 112 dma motorola introduction the dma can perform data transfers to and from any two cpu-addres- sable locations without cpu intervention. features features of the dma include the following: ? modular architecture ? service request-driven operation without cpu intervention ? three independent channels ? byte or word transfer capability ? block transfers and loop transfers ? cpu interrupt capability on completion of block transfer or on loop restart ? programmable dma bus bandwidth (25%, 50%, 67%, or 100% of total bus bandwidth) ? programmable dma service request/cpu interrupt request priority ? programmable dma enable during wait mode ? block transfers up to 256 bytes ? expandable architecture up to seven channels and eight transfer source inputs 2-dma_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dma functional description MC68HC708XL36 motorola dma 113 functional description the dma is a coprocessor for servicing peripheral devices that require data block transfers. for transmitting or receiving blocks of data to or from peripherals, dma transfers are faster and more code-efficient than cpu interrupts. the following tasks that contribute to cpu interrupt overhead are not part of a dma transfer: ? stacking and unstacking cpu registers ? loading interrupt vectors ? loading address pointers ? incrementing address pointers ? storing address pointers ? clearing interrupt flags ? returning from interrupt once the dma is initialized to transfer a block of data, a dma service request usually requires only two bus cycles per 8-bit byte or four cycles per 16-bit word to transfer the source data to a destination. figure 1 shows the structure of the dma. each dma channel can transfer data independently between any addresses in the memory map. 3-dma_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dma MC68HC708XL36 114 dma motorola figure 1. dma module block diagram register name bit 7 654321 bit 0 dma channel 0 source address register high (d0sh) read: ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 write: reset: indeterminate after reset dma channel 0 source address register low (d0sl) read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: reset: indeterminate after reset dma channel 0 destination address register high (d0dh) read: ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 write: reset: indeterminate after reset dma channel 0 destination address register low (d0dl) read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: reset: indeterminate after reset figure 2. i/o register summary channel 1 15 7 channel 0 channel 2 channel 0 channel 1 channel 2 0 channel 0 channel 1 channel 2 channel control block length byte count 70 70 channel 0 channel 1 channel 2 channel 0 channel 1 channel 2 0 destination address source address 15 0 alu in bus a in bus b internal bus out bus = bus switch system control logic registers registers registers registers registers temporary address temporary data dma service requests cpu interrupt request 4-dma_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dma functional description MC68HC708XL36 motorola dma 115 dma channel 0 control register (d0c) read: sdc3 sdc2 sdc1 sdc0 bwc dts2 dts1 dts0 write: reset: indeterminate after reset dma channel 0 block length register (d0bl) read: bl7 bl6 bl5 bl4 bl3 bl2 bl1 bl0 write: reset: indeterminate after reset dma channel 0 byte count register (d0bc) read: bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 write: reset: 00000000 dma channel 1 source address register high (d1sh) read: ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 write: reset: indeterminate after reset dma channel 1 source address register low (d1sl) read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: reset: indeterminate after reset dma channel 1 destination address register high (d1dh) read: ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 write: reset: indeterminate after reset dma channel 1 destination address register low (d1dl) read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: reset: indeterminate after reset dma channel 1 control register (d1c) read: sdc3 sdc2 sdc1 sdc0 bwc dts2 dts1 dts0 write: reset: indeterminate after reset dma channel 1 block length register (d1bl) read: bl7 bl6 bl5 bl4 bl3 bl2 bl1 bl0 write: reset: indeterminate after reset dma channel 1 byte count register (d1bc) read: bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 write: reset: 00000000 dma channel 2 source address register high (d2sh) read: ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 write: reset: indeterminate after reset dma channel 2 source address register low (d2sl) read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: reset: indeterminate after reset dma channel 2 destination address register high (d2dh) read: ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 write: reset: indeterminate after reset dma channel 2 destination address register low (d2dl) read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: reset: indeterminate after reset register name bit 7 654321 bit 0 figure 2. i/o register summary 5-dma_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dma MC68HC708XL36 116 dma motorola dma channel 2 control register (d2c) read: sdc3 sdc2 sdc1 sdc0 bwc dts2 dts1 dts0 write: reset: indeterminate after reset dma channel 2 block length register (d2bl) read: bl7 bl6 bl5 bl4 bl3 bll2 bl1 bl0 write: reset: indeterminate after reset dma channel 2 byte count register (d2bc) read: bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 write: reset: 00000000 dma control register 1 (dc1) read: bb1 bb0 tec2 iec2 tec1 iec1 tec0 iec0 write: reset: 00000000 dma status and control register (dsc) read: dmap l2 l1 l0 dmawe ifc2 ifc1 ifc0 write: reset: 00000000 dma control register 2 (dc2) read: swi7 swi6 swi5 swi4 swi33 swi2 swi1 swi0 write: reset: 00000000 table 1. i/o register address summary register d0sh d0sl d0dh d0dl d0c d0bl d0bc d1sh d1sl d1dh address $0034 $0035 $0036 $0037 $0038 $0039 $003b $003c $003d $003e register d1dl d1c d1bl d1bc d2sh d2sl d2dh d2dl d2c d2bl address $003f $0040 $0041 $0043 $0044 $0045 $0046 $0047 $0048 $0049 register d2bc dc1 dsc dc2 address $004b $004c $004d $004e register name bit 7 654321 bit 0 figure 2. i/o register summary 6-dma_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dma functional description MC68HC708XL36 motorola dma 117 dma/cpu timing when the dma transfers data, it takes control of the address bus, data bus, and r/ w line. during dma transfers, the cpu clock is suspended. the state of the cpu remains unchanged until the end of the dma transfer when the dma relinquishes control of the buses and r/ w line. then the cpu resumes operation as though nothing had happened. figure 3 and figure 4 show the timing of dma transfers. figure 3. single byte transfer timing (any dma bus bandwidth) data address cgmout 13 2456789 state bus bus 10 cpu-controlled bus cycle dma-controlled bus cycle r/ w 7-dma_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dma MC68HC708XL36 118 dma motorola figure 4. single word transfer timing (100% dma bus bandwidth) table 2. dma byte transfer activity state activity 1 dma service request occurs. 2 dma arbitrates channel priority. 3 dma generates internal control signals. 4 dma calculates source address. dma latches source address in temporary register. 5 dma drives source address onto address bus. dma drives r/ w line high. dma calculates destination address. dma latches destination address into temporary register. 6 dma latches source data into temporary register. dma increments byte count register. 7 dma drives destination address onto address bus. dma drives r/ w line low. dma subtracts byte count register from block length register. if difference = 0, dma disables channel by clearing tecx bit. if difference = 0 and iecx = 1, dma generates cpu interrupt request. 8 dma drives source data onto data bus. 9 dma releases address bus and r/ w line to cpu. 10 dma releases data bus to cpu. data address cgmout 13 2 4567 1112 state bus bus 13 cpu-controlled bus cycle dma-controlled bus cycle 10 9 8 14 15 16 r/ w 8-dma_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dma functional description MC68HC708XL36 motorola dma 119 table 3. dma word transfer activity state activity 1 dma service request occurs. 2 dma arbitrates channel priority. 3 dma generates internal control signals. 4 dma calculates low byte of source address. dma latches low byte of source address in temporary register. 5 dma drives low byte of source address onto address bus. dma drives r/ w line high. dma calculates low byte of destination address. dma latches low byte of destination address into temporary register. 6 dma latches low byte of source data into temporary register. dma increments byte count register. 7 dma drives low byte of destination address onto address bus. dma drives r/ w line low. dma subtracts byte count register from block length register. if difference = 0, dma disables channel by clearing tecx bit. if difference = 0 and iecx = 1, dma generates cpu interrupt request. 8 dma drives low byte of source data onto data bus. dma calculates high byte of source address. dma latches high byte of source address into temporary register. 9 dma drives the high byte of source address onto address bus. dma drives r/ w line high. dma calculates high byte of destination address. dma latches high byte of destination address in temporary register. 10 dma latches high byte of source data into temporary register. dma increments the byte count register. 11 dma drives high byte of destination address onto address bus. dma drives r/ w line low. dma subtracts byte count register from block length register. if difference = 0, dma disables channel by clearing tecx bit. if difference = 0 and iecx bit set, cpu receives interrupt request. 12 dma drives high byte of destination address onto address bus. 13 dma releases the address bus and r/ w line to cpu. 14 dma releases data bus to cpu. 9-dma_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dma MC68HC708XL36 120 dma motorola the following procedure shows how to program a dma transfer on a selected channel: 1. in dma control register 1 (dc1), disable the channel by clearing the tecx bit. (see dma control register 1 on page 133.) 2. in the source address registers (dxsh and dxsl), write the source base address. (see dma source address registers on page 143.) 3. in the destination address registers (dxdh and dxdl), write the destination base address. (see dma destination address registers on page 145.) 4. in the dma channel x control register (dxc), make the following selections (see dma channel control registers on page 140): a. select increment, decrement, or remain static for the source and destination addresses by writing to the source/destination address control bits, sdc[3:0]. b. select 8-bit or 16-bit data by writing to the byte/word control bit, bwc. c. assign a dma channel to the dma transfer source input by writing to the dma transfer source bits, dts[2:0]. 5. in the channel x dma block length register (dxbl), write the number of bytes to transfer. (see dma block length registers on page 146.) for word transfers, the block length number is two times the number of words. 6. in the dma status and control register (dsc), make the following selections (see dma status and control register on page 136): a. enable or disable looping of the source and destination addresses by writing to the loop enable bit, lx. b. select dma service request/cpu interrupt request priority by writing to the dma priority bit, dmap. c. enable or disable dma transfers during wait mode by writing to the dma wait enable bit, dmawe. 7. in dma control register 1 (dc1), make the following selections (see dma control register 1 on page 133): 10-dma_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dma functional description MC68HC708XL36 motorola dma 121 a. enable the dma channel x by writing to the transfer enable bit, tecx. b. enable or disable dma channel x to generate cpu interrupts on transfer completion by writing to the cpu interrupt enable bit, iecx. c. select the dma bus bandwidth by writing to the bus bandwidth control bits, bb0 and bb1. 8. to initiate the dma transfer with software, set the software initiate bit, swix, in dma control register 2 (dc2). (see dma control register 2 on page 139.) hardware-initiated dma service requests the following sources can generate dma service requests: ? timer interface module (tim) the tim can generate the following dma service requests: C tim channel 0 input capture/output compare C tim channel 1 input capture/output compare C tim channel 2 input capture/output compare C tim channel 3 input capture/output compare ? serial peripheral interface module (spi) the spi can generate the following dma service requests: C spi receiver full C spi transmitter empty ? serial communications interface module (sci) the sci can generate the following dma service requests: C sci receiver full C sci transmitter empty 11-dma_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dma MC68HC708XL36 122 dma motorola the dma has eight inputs for transfer sources. each dma transfer source input corresponds to one of the above dma service requests. to enable a transfer on one of the three dma channels, software must first assign the channel to one of the transfer source inputs. the channel control register of each channel determines its transfer source assignment. (see table 10. dma transfer source selection .) software-initiated dma service requests software can initiate a dma service request by writing to dma control register 2 (dc2). a software-initiated transfer begins when the following conditions are met: ? the channel is enabled by the channel x transfer enable bit, tecx, in dma control register 1 (dc1). ? the channel is assigned to a dma transfer source input by the dma transfer source bits, dts[2:0], in the channel x control register (dxc). ? the corresponding software initiate bit, swix, in dma control register 2 (dc2) is set, enabling a transfer on the transfer source input to which the channel is assigned. during a dma transfer on channel x, the channel x byte count register increments with every byte transferred. when the value in the channel x byte count register matches the value in the channel x block length register, the channel x cpu interrupt flag, ifcx, becomes set. if the channel x cpu interrupt enable bit, iecx, is also set, the dma issues a cpu interrupt request. dma latency when one dma channel is active, the normal dma latency is two cycles. writing to the destination/source address registers, the channel control registers, or the block length registers of another dma channel during a transfer adds three cycles to dma latency. if more than one dma channel is active, the latency of lower-priority channels increases. if two or more dma channels have pending service requests, at least one cpu cycle executes between each channel transfer. 12-dma_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dma functional description MC68HC708XL36 motorola dma 123 dma source/destination address calculation three 16-bit buses connect the 16-bit dma arithmetic/logic unit (alu) to the dma channel registers. during a dma transfer, the dma alu: ? calculates the transfer source and transfer destination addresses. ? increments the dma byte count register for each byte transferred. ? determines when a block or loop transfer is complete by comparing the dma byte count register with the value programmed in the dma block length register. the dma source address register and destination address register contain the base addresses for a dma transfer. the dma alu uses these address registers as base pointers when it starts the transfer. the dma byte count register contains the number of bytes transferred in the current dma operation. the dma alu uses the source/destination address registers and the byte count register to calculate the actual source and destination addresses in the following manner: ? when an address is configured to increment, the dma alu adds the byte count register to the base address. ? when an address is configured to decrement, the dma alu subtracts the byte counter register from the base address. ? when an address is configured to remain static, the dma alu uses the base address as is. the dma can be programmed to: ? stop the transfer after a number of bytes is transferred or ? after a number of bytes is transferred, loop back to the base addresses and continue the transfer. figure 5 through figure 13 show how the dma calculates source and destination addresses. 13-dma_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dma MC68HC708XL36 124 dma motorola figure 5. decremented source and decremented destination figure 6. incremented source and incremented destination 15 channel x source base address 0 15 channel x destination base address 0 channel x byte count 70 channel x control 70 channel x block length 70 C C + 1 = ? source address destination addres s when byte count = block length, the cpu interrupt flag (ifcx) is set and the byte count is reset. if in loop mode (lx = 1), leave tecx set. if in finite transfer mode (lx = 0), clear tecx . note: 15 channel x source base address 0 15 channel x destination base address 0 channel x byte count 70 channel x control 70 channel x block length 70 + + + 1 = ? source address destination address when byte count = block length, the cpu interrupt flag (ifcx) is set and the byte count is reset. if in loop mode (lx = 1), leave tecx set. if in finite transfer mode (lx = 0), clear tecx. note: 14-dma_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dma functional description MC68HC708XL36 motorola dma 125 figure 7. static source and decremented destination figure 8. decremented source and static destination 15 channel x source base address 0 15 channel x destination base address 0 channel x byte count 70 channel x control 70 channel x block length 70 C + 1 = ? source address destination address when byte count = block length, the cpu interrupt flag (ifcx) is set and the byte count is reset. if in loop mode (lx = 1), leave tecx set. if in finite transfer mode (lx = 0), clear tecx. note: 15 channel x source base address 0 15 channel x destination base address 0 channel x byte count 70 channel x control 70 channel x block length 70 C + 1 = ? source address destination address when byte count = block length, the cpu interrupt flag (ifcx) is set and the byte count is reset. if in loop mode (lx = 1), leave tecx set. if in finite transfer mode (lx = 0), clear tecx. note: 15-dma_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dma MC68HC708XL36 126 dma motorola figure 9. static source and incremented destination figure 10. incremented source and static destination 15 channel x source base address 0 15 channel x destination base address 0 channel x byte count 70 channel x control 70 channel x block length 70 + + 1 = ? source address destination address when byte count = block length, the cpu interrupt flag (ifcx) is set and the byte count is reset. if in loop mode (lx = 1), leave tecx set. if in finite transfer mode (lx = 0), clear tecx. note: 15 channel x source base address 0 15 channel x destination base address 0 channel x byte count 70 channel x control 70 channel x block length 70 + + 1 = ? source address destination address when byte count = block length, the cpu interrupt flag (ifcx) is set and the byte count is reset. if in loop mode (lx = 1), leave tecx set. if in finite transfer mode (lx = 0), clear tecx. note: 16-dma_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dma functional description MC68HC708XL36 motorola dma 127 figure 11. decremented source and incremented destination figure 12. incremented source and decremented destination 15 channel x source base address 0 15 channel x destination base address 0 channel x byte count 70 channel x control 70 channel x block length 70 + C + 1 = ? source address destination address when byte count = block length, the cpu interrupt flag (ifcx) is set and the byte count is reset. if in loop mode (lx = 1), leave tecx set. if in finite transfer mode (lx = 0), clear tecx. note: 15 channel x source base address 0 15 channel x destination base address 0 channel x byte count 70 channel x control 70 channel x block length 70 C + + 1 = ? source address destination address when byte count = block length, the cpu interrupt flag (ifcx) is set and the byte count is reset. if in loop mode (lx = 1), leave tecx set. if in finite transfer mode (lx = 0), clear tecx. note: 17-dma_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dma MC68HC708XL36 128 dma motorola figure 13. static source and static destination 1. s = source base address 2. d = destination base address table 4. dma address calculation (byte mode) static source static destination incremented source static destination static source incremented destination decremented source static destination static source decremented destination byte from to from to from to from to from to 1s (1) d (2) sds d s ds d 2 s d s +1 d s d +1 s C1 d s d C1 3 s d s +2 d s d +2 s C2 d s d C2 4 s d s +3 d s d +3 s C3 d s d C3 n s d s +n C1 d s d +n C1 s C(n C1) d s d C(n C1) 15 channel x source base address 0 15 channel x destination base address 0 channel x byte count 70 channel x control 70 channel x block length 70 + 1 = ? source address destination address when byte count = block length, the cpu interrupt flag (ifcx) is set and the byte count is reset. if in loop mode (lx = 1), leave tecx set. if in finite transfer mode (lx = 0), clear tecx. note: 18-dma_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dma functional description MC68HC708XL36 motorola dma 129 1. s = source base address 2. d = destination base address table 5. dma address calculation (word mode) static source static destination incremented source static destination static source incremented destination decremented source static destination static source decremented destination word byte from to from to from to from to from to 1 1s (1) d (2) sds d s ds d 2 s +1 d +1 s +1 d +1 s +1 d +1 s C1 d +1 s +1 d C1 2 3 s d s +2 d s d +2 s C2 d s d C2 4 s +1 d +1 s +3 d +1 s +1 d +3 s C3 d +1 s +1 d C3 3 5 s d s +4 d s d +4 s C4 d s d C4 6 s +1 d +1 s +5 d +1 s +1 d +5 s C5 d +1 s +1 d C5 n 2n C1 s d s +2n C2 d s d +2n C2 s C(2n C2) d s d C(2n C2) 2n s +1 d +1 s +2n C1 d +1 s +1 d +2n C1 s C(2n C1) d +1 s +1 d C(2n C1) 19-dma_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dma MC68HC708XL36 130 dma motorola low-power modes the wait and stop instructions put the mcu in low-power-consump- tion standby modes. wait mode if enabled by the dmawe bit in the dma status and control register, the dma remains active in wait mode. the dma can transfer data to and from peripherals while the mcu remains in wait mode. if the wait instruction occurs during a dma transfer while dmawe is set, the dma transfer continues to completion. if the dmawe bit is clear, a wait instruction suspends the current dma transfer. if the dma priority bit (dmap) is set, the suspended transfer resumes when the mcu exits wait mode. stop mode the dma is inactive during stop mode. a stop instruction suspends any dma transfer in progress. if an external interrupt brings the mcu out of stop mode and the dma priority bit (dmap) is set, the suspended dma transfer resumes. if a reset brings the mcu out of stop mode, the transfer is aborted. entering stop mode when a dma channel is enabled may fail to clear the the interrupt mask (i bit) in the condition code register. to make sure the i bit is cleared when entering stop mode: ? before executing the stop instruction, wait until any current dma transfer is complete. then disable dma transfers by clearing bits tec[2:0] in dma control register 1. or, ? execute the clear-interrupt-mask instruction (cli) before entering stop mode. 20-dma_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dma dma during break interrupts MC68HC708XL36 motorola dma 131 dma during break interrupts if the dma is enabled, clear the dmap bit in the dma status and control register before executing a break interrupt. if a dma-generated address matches the contents of the break address registers, a break interrupt begins at the end of the current cpu instruction. if a break interrupt is asserted during the current address cycle and the dma is active, the dma releases the internal address and data buses at the next address boundary to preserve the current mcu state. during the break interrupt, the dma continues to arbitrate dma channel priorities. after the break interrupt, the dma becomes active again and resumes transferring data according to its highest priority service request. the bcfe bit in the break flag control register (bfcr) enables software to clear status bits during the break state. (see break module on page 149.) to allow software to clear status bits during a break interrupt, write a logic 1 to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break state, write a logic 0 to the bcfe bit. with bcfe at logic 0 (its default state), software can read and write i/o registers during the break state without affecting status bits. some status bits have a two-step read/write clearing procedure. if software does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is at logic 0. after the break, doing the second step clears the status bit. 21-dma_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dma MC68HC708XL36 132 dma motorola dma registers the following registers control and monitor operation of the dma: ? dma control register 1 (dc1) ? dma status and control register (dsc) ? dma control register 2 (dc2) dc1, dsc, and dc2 can be written during a dma transfer without affecting dma latency. the following registers control operation of each of the dma channels: ? dma source address registers, high and low (d0sh:d0sl, d1sh:d1sl, and d2sh:d2sl) ? dma destination address registers, high and low (d0dh:d0dl, d1dh:d1dl, and d2dh:d2dl) ? dma channel x control registers (d0cCd2c) ? dma channel x byte count registers (d0bcCd2bc) ? dma channel x block length registers (d0blCd2bl) writing to dxsh:dxsl, dxdh:dxdl, dxc, and dxbl during a transfer affects dma latency. a write to a channel x control register during a transfer has a two-bus cycle latency if the transfer is first suspended by disabling the channel. disable the channel by writing a 0 to the tecx bit in dma control register 1. without first suspending the transfer, a write to a channel x control register during a transfer has a three-bus cycle latency. 22-dma_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dma dma registers MC68HC708XL36 motorola dma 133 dma control register 1 dma control register 1: ? enables channels to transfer data when dma service requests occur. ? enables channels to generate cpu interrupt requests. ? controls how much of the bus bandwidth the dma uses. bb1 and bb0 bus bandwidth control bits these read/write bits control the ratio of dma/cpu bus activity during a dma transfer. as table 6 shows, the dma can use 25%, 50%, 67%, or 100% of the bus bandwidth. reset clears bits bb1 and bb0. figure 15 , figure 16 , and figure 17 show the timing of dma transfers with dma bus bandwidths of 25%, 50%, and 67%. address: $004c bit 7 654321 bit 0 read: bb1 bb0 tec2 iec2 tec1 iec1 tec0 iec0 write: reset: 00000000 figure 14. dma control register 1 (dc1) table 6. dma/cpu bus control selection dma transfer bb1:bb0 dma bus cycles cpu bus cycles 00 2 (25%) 6 (75%) 01 2 (50%) 2 (50%) 10 2 (67%) 1 (33%) 11 all (100%) 0 (0%) 23-dma_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dma MC68HC708XL36 134 dma motorola figure 15. multiple byte/word transfer timing: 25% dma bus bandwidth figure 16. multiple byte/word transfer timing: 50% dma bus bandwidth figure 17. multiple byte/word transfer timing: 67% dma bus bandwidth note: when two or more dma channels have transfers pending, the cpu executes at least one cycle between each dma block length, even if the dma channels have 100% of the bus bandwidth. data address cgmout bus bus cpu-controlled bus cycle dma-controlled bus cycle r/ w data address cgmout bus bus cpu-controlled bus cycle dma-controlled bus cycle r/ w data address cgmout bus bus cpu-controlled bus cycle dma-controlled bus cycle r/ w 24-dma_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dma dma registers MC68HC708XL36 motorola dma 135 for dma transfers of one byte or one word, giving the dma 100% of the bus bandwidth is appropriate. however, for large, software-initiated transfers, limiting the bus bandwidth of the dma may be useful to keep from slowing cpu activity. tec[2:0] transfer enable bits these read/write bits enable the corresponding channels to perform transfers when dma service requests occur. when two or more channels are enabled, a transfer on one channel cannot begin while another channel is transferring a byte or word. reset clears the tec[2:0] bits. 1 = corresponding dma channel enabled 0 = corresponding dma channel disabled iec[2:0] cpu interrupt enable bits these read/write bits enable the corresponding channels to generate cpu interrupt requests upon completion of dma block transfers or at the restart of dma transfer loops. reset clears the iec[2:0] bits. 1 = cpu interrupts from corresponding channel enabled 0 = cpu interrupts from corresponding channel disabled 25-dma_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dma MC68HC708XL36 136 dma motorola dma status and control register the dma status and control register: ? flags completion of dma transfers. ? controls looping of source and destination address counts. ? controls priority of dma service requests and cpu interrupt requests. dmap dma priority bit this read/write bit controls the priority of cpu interrupt requests during dma transfers. reset clears the dmap bit. 1 = cpu interrupt requests inhibited during dma transfers when dmap is set, a cpu interrupt request is not recognized until the end of the current dma transfer. during a block transfer, the increase in cpu interrupt latency depends on the block size and on the bus bandwidth bits, bb[1:0]. (see dma control register 1 on page 133.) 0 = cpu interrupt requests recognized during dma transfers when dmap is clear, a cpu interrupt request is recognized after the transfer of the current byte or word in the current dma transfer. the cpu interrupt disables the dma by clearing the transfer enable bits, tec[2:0]. (see dma control register 1 on page 133.) the dma can increase cpu interrupt latency by up to three cycles in a byte transfer or five cycles in a word transfer. note: when dmap = 0, a cpu interrupt clears the tecx bit if the channel has a pending dma transfer. software must re-enable channel x after each cpu interrupt by setting the tecx bit. address: $004d bit 7 654321 bit 0 read: dmap l2 l1 l0 dmawe ifc2 ifc1 ifc0 write: reset: 00000000 figure 18. dma status and control register (dsc) 26-dma_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dma dma registers MC68HC708XL36 motorola dma 137 table 7 shows the effect of the dmap bit when the dma has 100% of the bus bandwidth (bb[1:0] = 1:1). l[2:0] loop enable bits these read/write bits enable looping of the dma back to the base addresses in the source address and destination address registers during block transfers. reset clears the l[2:0] bits. 1 = looping enabled after transferring the number of bytes equal to the number programmed in the dma block length register, the dma: ? sets the cpu interrupt flag (ifcx) for that channel. ? generates a cpu interrupt request if enabled (iecx = 1). ? clears the byte count register. ? continues the transfer from the base address. 0 = looping disabled after transferring the number of bytes equal to the number programmed in the dma block length register, the dma: ? sets the cpu interrupt flag (ifcx) for that channel. ? generates a cpu interrupt request if enabled (iecx = 1). ? clears the byte count register. ? disables the channel by clearing the tecx bit. note: the cpu executes a minimum of one cycle before the next dma loop begins, even if the dma has 100% of the bus bandwidth. table 7. dma transfer/cpu interrupt request priority selection dmap = 0 dmap = 1 highest priority cpu interrupt requests dma channel 0 transfer dma channel 0 transfer dma channel 1 transfer dma channel 1 transfer dma channel 2 transfer lowest priority dma channel 2 transfer cpu interrupt requests 27-dma_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dma MC68HC708XL36 138 dma motorola dmawe dma wait enable bit this read/write bit enables the dma to operate while in wait mode. reset clears the dmawe bit. 1 = dma transfer enabled after wait instruction 0 = dma transfer suspended after wait instruction ifc[2:0] cpu interrupt flag bits these read/write bits become set when a dma transfer is complete or at the end of each transfer loop. ifc2, ifc1, or ifc0 can generate a cpu interrupt request if the corresponding iecx bit is set in dma control register 1. clear ifc[2:0] by reading them and then writing 0s to them. reset clears the ifc[2:0] bits. 1 = dma transfer complete 0 = dma transfer not complete 28-dma_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dma dma registers MC68HC708XL36 motorola dma 139 dma control register 2 dma control register 2 can perform two functions: ? initiate dma transfers through software ? simulate dma service requests for test purposes swi[7:0] software initiate bits each of these read/write bits corresponds to one of the eight dma transfer sources. (see table 10 on page 142.) setting an swix bit can initiate a dma service request from the selected transfer source. 1 = dma software transfer initiated 0 = dma software transfer halted or not initiated use the following steps to generate a software-initiated dma service request: 1. enable a channel to perform a transfer by setting its tecx bit. (see dma control register 1 on page 133.) 2. assign the channel to a dma transfer source by writing a binary value from 000 to 111 to its dts[2:0] bits. (see dma channel control registers on page 140.) 3. set the swix bit that corresponds to the selected transfer source. the bit positions (0C7) of the swix bits correspond to the binary values (000C111) that select the dma transfer source. for example, after selecting transfer source 100 (binary), set bit swi4 to initiate the dma service request. address: $004e bit 7 654321 bit 0 read: swi7 swi6 swi5 swi4 swi3 swi2 swi1 swi0 write: reset: 00000000 figure 19. dma control register 2 (dc2) 29-dma_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dma MC68HC708XL36 140 dma motorola dma channel control registers each dma channel control register: ? controls calculation of source and destination addresses. ? selects transfer of 8-bit bytes or 16-bit words on the channel. ? assigns the channel to one of eight dma transfer sources. the state of the dma channel control registers after reset is indeterminate. sdc[3:0] source/destination address control bits these read/write bits control calculation of the source and destination addresses as shown in table 9 . bit 7 654321 bit 0 read: sdc3 sdc2 sdc1 sdc0 bwc dts2 dts1 dts0 write: reset: indeterminate after reset figure 20. dma channel control registers (d0cCd2c) table 8. dma channel control register address summary register d0c d1c d2c address $0038 $0040 $0048 table 9. source/destination address register control sdc[3:0] source address destination address 1010 increment increment 1001 increment decrement 1000 increment static 0110 decrement increment 0101 decrement decrement 0100 decrement static 0010 static increment 0001 static decrement 0000 static static 30-dma_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dma dma registers MC68HC708XL36 motorola dma 141 the dma calculates an incremented address by adding the byte count register to the base address. to calculate a decremented address, the dma subtracts the byte count register from the base address. to determine a static address, the dma reads the base address. bwc byte/word control bit this read/write bit determines whether the dma channel transfers 8-bit bytes or 16-bit words. the bwc bit has no effect unless either the source or destination address is static or both are static. 1 = 16-bit words 0 = 8-bit bytes note: to transfer a block of 16-bit words (bwc = 1), set the block length to the number of words times two. (see dma block length registers on page 146.) when both the source and destination addresses are static, the first byte of the word transfers from the source base address to the destination base address. the second byte transfers from the source base address plus one to the destination address plus one. when either the source or destination address increments or decrements, the dma transfers bytes from or to incrementing or decrementing addresses. the cpu interrupt flag (ifcx) becomes set when the byte count register equals the block length register. dts[2:0] dma transfer source bits these read/write bits assign the dma channels to the eight transfer source inputs as shown in table 10 . 31-dma_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dma MC68HC708XL36 142 dma motorola table 10. dma transfer source selection transfer source dts2:dts1:dts0 tim channel 0 interrupt request 000 tim channel 1 interrupt request 001 tim channel 2 interrupt request 010 tim channel 3 interrupt request 011 spi receive interrupt request 100 spi transmit interrupt request 101 sci receive interrupt request 110 sci transmit interrupt request 111 32-dma_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dma dma registers MC68HC708XL36 motorola dma 143 dma source address registers each dma channel takes its data from a source base address contained in a 16-bit source address register. during a block transfer, the dma determines successive source addresses by adding to (to increment) or subtracting from (to decrement) the base address. in static address transfers, the dma finds the source address by merely reading the source address registers. figure 21 shows the dma source address registers. the state of the source address registers after reset is indeterminate. 33-dma_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dma MC68HC708XL36 144 dma motorola bit 7 654321 bit 0 read: ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 write: reset: indeterminate after reset bit 7 654321 bit 0 read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: reset: indeterminate after reset figure 21. dma source address registers (d0sh/lCd2sh/l) table 11. dma source address register address summary register d0sh d0sl d1sh d1sl d2sh d2sl address $0034 $0035 $003c $003d $0044 $0045 34-dma_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dma dma registers MC68HC708XL36 motorola dma 145 dma destination address registers each dma channel transfers data to the destination base address contained in a 16-bit destination address register. during a block transfer, the dma determines successive destination addresses by adding to (to increment) or subtracting from (to decrement) the base address. in static address transfers, the dma finds the destination address by merely reading the destination address registers. figure 22 shows the dma destination address registers. the state of the destination address registers after reset is indeterminate. bit 7 654321 bit 0 read: ad15 ad14 ad13 ad12 ad11 ad10 ad9 ad8 write: reset: indeterminate after reset bit 7 654321 bit 0 read: ad7 ad6 ad5 ad4 ad3 ad2 ad1 ad0 write: reset: indeterminate after reset figure 22. dma destination address registers (d0dh/lCd2dh/l) table 12. destination address register address summary register d0dh d0dl d1dh d1dl d2dh d2dl address $0036 $0037 $003e $003f $0046 $0047 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dma MC68HC708XL36 146 dma motorola dma block length registers the read/write block length registers control the number of bytes transferred. during a block transfer, the dma compares the number programmed into the channels dma block length register to the number in its dma byte count register. when the byte count reaches the value in the block length register, the dma: ? sets the cpu interrupt flag (ifcx) for that channel in the dma status and control register. ? generates a cpu interrupt request if enabled. ? resets the byte count register. if looping is disabled (lx bit in dma status and control register = 0), the dma then stops the transfer by clearing the tecx bit in dma control register 1, disabling the channel. if looping is enabled (lx bit = 1), the dma continues the transfer from the base address. the block length of a word transfer is twice the number of words. the state of the dma block length registers after reset is indeterminate. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dma dma registers MC68HC708XL36 motorola dma 147 bit 7 654321 bit 0 read: bl7 bl6 bl5 bl4 bl3 bl2 bl1 bl0 write: reset: indeterminate after reset figure 23. dma block length registers (d0blCd2bl) table 13. dma block length register address summary register d0bl d1bl d2bl address $0039 $0041 $0049 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . dma MC68HC708XL36 148 dma motorola dma byte count registers each read/write dma byte count register contains the number of bytes transferred on that channel in the current dma transfer. writing to the channel x source address or destination address register clears the channel x byte count register. the channel x byte count register also is cleared when its count reaches the value in the channel x block length register. reset clears the byte count registers. bit 7 654321 bit 0 read: bc7 bc6 bc5 bc4 bc3 bc2 bc1 bc0 write: reset: 00000000 figure 24. dma byte count registers (d0bcCd2bc) table 14. dma byte count register address summary register d0bc d1bc d2bc address $003b $0043 $004b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC708XL36 motorola brk 149 break module brk contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .149 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .150 flag protection during break interrupts . . . . . . . . . . . . . . . . . . . .152 cpu during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . .152 dma during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . .152 tim during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . .152 cop during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . .152 low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153 stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153 break module registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .153 break status and control register . . . . . . . . . . . . . . . . . . . . . . . .154 break address registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155 break status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .155 break flag control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . .156 introduction the break module can generate a break interrupt that stops normal program flow at a defined address to enter a background program. 1-brk_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . brk MC68HC708XL36 150 brk motorola features ? accessible i/o registers during break interrupts ? cpu-generated and dma-generated break interrupts ? software-generated break interrupts ? cop disabling during break interrupts functional description when the internal address bus matches the value written in the break address registers, the break module issues a breakpoint signal to the cpu. the cpu then loads the instruction register with a software interrupt instruction (swi) after completion of the current cpu instruction. the program counter vectors to $fffc and $fffd ($fefc and $fefd in monitor mode). the following events can cause a break interrupt to occur: ? a cpu-generated address (the address in the program counter) matches the contents of the break address registers. ? during a dma transfer, a dma-generated address matches the contents of the break address registers. ? software writes a logic 1 to the brka bit in the break status and control register. when a cpu- or dma-generated address matches the contents of the break address registers, the break interrupt begins after the cpu completes its current instruction. a return-from-interrupt instruction (rti) in the break routine ends the break interrupt and returns the mcu to normal operation. figure 1 shows the structure of the break module. 2-brk_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . brk functional description MC68HC708XL36 motorola brk 151 figure 1. break module block diagram register name bit 7 654321 bit 0 break status register (bsr) read: 000100bw0 write: rrrrrr0r reset: 00010000 break flag control register (bfcr) read: bfce rrrrrrr write: reset: 0 break address register high (brkh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 00000000 break address register low (brkl) read: bit 7 654321 bit 0 write: reset: 00000000 break status and control register (bscr) read: brke brka 000000 write: reset: 00000000 = unimplemented r = reserved figure 2. i/o register summary table 1. i/o register address summary register bsr bfcr brkh brkl bscr address $fe00 $fe03 $fe0c $fe0d $fe0e iab[15:8] iab[7:0] 8-bit comparator 8-bit comparator control break address register low break address register high iab[15:0] break 3-brk_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . brk MC68HC708XL36 152 brk motorola flag protection during break interrupts the bcfe bit in the break flag control register (bfcr) enables software to clear status bits during the break state. cpu during break interrupts the cpu starts a break interrupt by: ? loading the instruction register with the swi instruction. ? loading the program counter with $fffc:$fffd ($fefc:$fefd in monitor mode). the break interrupt begins after completion of the cpu instruction in progress. if the break address register match occurs on the last cycle of a cpu instruction, the break interrupt begins immediately. dma during break interrupts if the dma is enabled, clear the dmap bit in the dma status and control register before executing a break interrupt. if a break interrupt is asserted during the current address cycle and the dma is active, the dma releases the internal address and data buses at the next address boundary to preserve the current mcu state. during the break interrupt, the dma continues to arbitrate dma channel priorities. after the break interrupt, the dma becomes active again and resumes transferring data according to its highest priority service request. tim during break interrupts a break interrupt stops the timer counter. cop during break interrupts the cop is disabled during a break interrupt when v dd +v hi is present on the rst pin. 4-brk_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . brk low-power modes MC68HC708XL36 motorola brk 153 low-power modes the wait and stop instructions put the mcu in low-power-consump- tion standby modes. wait mode if enabled, the break module is active in wait mode. a dma-generated address that matches the break address registers in wait mode sets the bw in the break status register. the dma can also use the break status and control register as its destination address in order to write to the brka and brke bits during wait mode. a dma write to the break status and control register sets the bw bit. stop mode the break module is inactive in stop mode. the stop instruction does not affect break module register states. break module registers these registers control and monitor operation of the break module: ? break status and control register (bscr) ? break address register high (brkh) ? break address register low (brkl) ? break status register (bsr) ? break flag control register (bfcr) 5-brk_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . brk MC68HC708XL36 154 brk motorola break status and control register the break status and control register contains break module enable and status bits. brke break enable bit this read/write bit enables breaks on break address register matches. clear brke by writing a logic 0 to bit 7. reset clears the brke bit. 1 = breaks enabled on 16-bit address match 0 = breaks disabled on 16-bit address match brka break active bit this read/write status and control bit is set when a break address match occurs. writing a logic 1 to brka generates a break interrupt. clear brka by writing a logic 0 to it before exiting the break routine. reset clears the brka bit. 1 = (when read) break address match 0 = (when read) no break address match address: $fe0e bit 7 654321 bit 0 read: brke brka 000000 write: reset: 00000000 = unimplemented figure 3. break status and control register (bscr) 6-brk_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . brk break module registers MC68HC708XL36 motorola brk 155 break address registers the break address registers contain the high and low bytes of the desired breakpoint address. reset clears the break address registers. break status register the break status register contains a flag to indicate that a break caused an exit from wait mode. the flag is useful in applications requiring a return to wait mode after exiting from a break interrupt. bw break wait bit this read/write bit is set when a break interrupt causes an exit from wait mode. clear bw by writing a logic 0 to it. reset clears bw. 1 = break interrupt during wait mode 0 = no break interrupt during wait mode register: brkh brkl address: $fe0c $fe0d bit 7 654321 bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 00000000 read: bit 7 654321 bit 0 write: reset: 00000000 figure 4. break address registers (brkh and brkl) address: $fe00 bit 7 654321 bit 0 read: 000100bw0 write: rrrrrrnoter reset: 00010000 r = reserved note: writing a logic 0 clears bw. figure 5. break status register (bsr) 7-brk_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . brk MC68HC708XL36 156 brk motorola bw is for applications that require a return to wait mode after exiting wait mode for a dma-generated break interrupt. bw can be read within the break interrupt routine. the user can modify the return address on the stack by subtracting 1 from it. the following code is an example. break flag control register the break flag control register contains a bit that enables software to clear status bits while the mcu is in a break state. bcfe break clear flag enable bit this read/write bit enables software to clear status bits by accessing status registers while the mcu is in a break state. to clear status bits during the break state, the bcfe bit must be set. 1 = status bits clearable during break 0 = status bits not clearable during break ; ; ; this code works if the h register was stacked in the break interrupt routine. execute this code at the end of the break interrupt routine. hibyte equ 5 lobyte equ 6 ; if not bw, do rti brclr bw,bsr, return ; ; see if wait mode or stop mode was exited by break. tst lobyte,sp ; if returnlo is not 0, bne dolo ; then just decrement low byte. dec hibyte,sp ; else deal with high byte also. dolo dec lobyte,sp ; point to wait/stop opcode. return pulh rti ; restore h register. address: $fe03 bit 7 654321 bit 0 read: bcfe rrrrrrr write: reset: 0 r = reserved figure 6. break flag control register (bfcr) 8-brk_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC708XL36 motorola mon 157 monitor rom mon contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .157 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .158 entering monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .160 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162 break signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162 baud rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .162 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .163 security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .169 introduction execution of code in the monitor rom in monitor mode allows complete testing of the mcu through a single-wire interface with a host computer. 1-mon08sp_1p f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mon MC68HC708XL36 158 mon motorola features features of monitor mode include the following: ? normal user-mode pin functionality ? one pin dedicated to serial communication between monitor rom and host computer ? standard mark/space non-return-to-zero (nrz) communication with host computer ? execution of code in either ram or eprom ? eprom programming ? eprom security functional description the monitor rom receives and executes commands from a host. figure 1 shows an example circuit used to enter monitor mode and communicate with a host via a standard rs-232 interface. simple monitor commands can access any memory address. in monitor mode, the mcu can execute the code in ram loaded by the host while all mcu pins retain normal operating mode functions. all communication between the host and the mcu is through the pa0 pin at a chosen baud rate. a level-shifting and multiplexing interface is required between pa0 and the host. pa0 is used in a wired-or configuration and requires a pullup resistor. 2-mon08sp_1p f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mon functional description MC68HC708XL36 motorola mon 159 figure 1. monitor mode circuit 10 m w x1 v dd v dda v dd + v hi v dd mc145407 mc74hc125 rst irq1 irq2 v dda cgmxfc osc1 osc2 cgnd v ss v dd pa0 v dd 10 k w 0.1 m f 0.1 m f 10 k w 10 w 6 5 db-25 2 3 7 20 18 17 19 16 15 v dd v dd v dd 20 pf 20 pf 10 m f 10 m f 10 m f 10 m f 1 2 4 7 14 3 0.1 m f 4.9152 mhz 10 k w pc3 v dd 10 k w b a note: position a bus clock = cgmxclk ? 4 or cgmvclk ? 4 position b bus clock = cgmxclk ? 2 see note. 5 6 v dd 10 k w pc0 pc1 0.1 m f pa7 + + 1 + + 3 4 2 10 k w 10 k w 10 k w 3-mon08sp_1p f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mon MC68HC708XL36 160 mon motorola entering monitor mode table 1 shows the pin conditions for entering monitor mode. if the pc3 pin is low upon monitor mode entry, the bus frequency is equal to the frequency of cgmxclk divided by two. cgmxclk is a buffered version of the clock on the osc1 pin. if pc3 is high upon monitor mode entry, the bus frequency is equal to the frequency of cgmxclk divided by four. the pll can be engaged after monitor mode entry to multiply the bus frequency by programming the cgm. for information on how to program the pll, see clock generator module on page 83. to use the pll, pc3 must be high during monitor mode entry. with the pll engaged, the bus frequency is equal to the pll output, cgmvclk, divided by four. note: if cgmxclk divided by two is selected as the bus frequency (pc3 = 0), the osc1 signal must have a 50% duty cycle at maximum bus frequency. enter monitor mode with one of the pin configurations shown in table 1 by pulling rst low and then high. the rising edge of rst latches monitor mode. once monitor mode is latched, the values on the pc0, pc1, pa0, and pc3 pins can be changed. note: the pa7 pin must remain at logic 0 for 24 bus cycles after the rst pin goes high. table 1. monitor mode entry irq pin pa7 pin pc0 pin pc1 pin pa0 pin pc3 pin bus clock frequency v dd + v hi 0101 1 or 0 cgmxclk 4 ----------------------------- cgmvclk 4 ----------------------------- cgmxclk 2 ----------------------------- 4-mon08sp_1p f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mon functional description MC68HC708XL36 motorola mon 161 once out of reset, the mcu waits for the host to send eight security bytes. (see security on page 169.) after the security bytes, the mcu sends a break signal (10 consecutive logic 0s) to the host, indicating that it is ready to receive a command. in monitor mode, the mcu uses different vectors for reset, swi, and break interrupt than those for user mode. the alternate vectors are in the $fe page instead of the $ff page and allow code execution from the internal monitor firmware instead of user code. the cop module is disabled in monitor mode as long as v dd +v hi is applied to either the irq pin or the rst pin. table 2 summarizes the differences between user mode and monitor mode. 1. if the high voltage (v dd + v hi ) is removed from the irq pin or the rst pin, the cop is enabled. the cop is a mask option enabled or disabled by the copd bit in the config- uration register. table 2. mode differences modes functions cop reset vector high reset vector low break vector high break vector low swi vector high swi vector low user enabled $fffe $ffff $fffc $fffd $fffc $fffd monitor disabled (1) $fefe $feff $fefc $fefd $fefc $fefd 5-mon08sp_1p f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mon MC68HC708XL36 162 mon motorola data format communication with the monitor rom is in standard non-return-to-zero (nrz) mark/space data format. transmit and receive baud rates must be identical. figure 2. monitor data format break signal a start bit (logic 0) followed by nine logic 0 bits is a break signal. when the monitor receives a break signal, it drives the pa0 pin high for the duration of two bits and then echos back the break signal. figure 3. break transaction baud rate the bus clock frequency of the mcu in monitor mode is determined by: ? the external clock frequency ? the value on the pc3 pin ? whether the phase-locked loop (pll) is engaged the internal monitor firmware performs a division by 256 (for sampling data); therefore, the bus frequency divided by 256 is the baud rate of the monitor mode data transfer. for example, with a 4.9152-mhz external clock and the pc3 pin at logic 1 during reset, data is transferred between the monitor and host at 4800 baud. if the pc3 pin is at logic 0 during reset, the monitor baud rate is 9600. bit 5 start bit bit 0 bit 1 stop bit bit 2 bit 3 bit 4 bit 6 bit 7 0 no stop bit 2-bit delay time before 0 echo pa0 bit time start 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 6-mon08sp_1p f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mon functional description MC68HC708XL36 motorola mon 163 the pll can be engaged to increase the baud rate of instruction transfer between the host and the mcu and to increase the speed of program execution. monitor mode must be entered with ptc high to use the pll. see entering monitor mode on page 160. initially, the bus frequency is a divide-by-four of the input clock. after the pll is programmed and selected as the base clock, communication between the host and mcu must be re-established at the new baud rate. one way to accomplish this is with a program downloaded from the host into the mcu ram. the downloaded routine can program the pll and send a new baud rate flag to the host just before engaging the pll onto the bus. then an swi instruction can be used to return program control to the monitor firmware. commands the monitor rom firmware uses the following commands: ? read (read memory) ? write (write memory) ? iread (indexed read) ? iwrite (indexed write) ? readsp (read stack pointer + 1) ? run (run user program) the monitor rom firmware echoes each received byte back to the pa0 pin for error checking. an 11-bit delay at the end of each command allows the host to send a break character to cancel the command. a delay of two bit times occurs before each echo and before read, iread, or readsp data is returned. the data returned by a read command appears after the echo of the last byte of the command. note: wait one bit time after each echo before sending the next byte. 7-mon08sp_1p f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mon MC68HC708XL36 164 mon motorola figure 4. read transaction figure 5. write transaction read read echo from host address high address high address low address low data return 1 3, 2 11 4 4 note: 1 = echo delay (2 bit times) 2 = data return delay (2 bit times) 3 = cancel command delay (11 bit times) 4 = wait 1 bit time before sending next byte. 44 write write echo from host address high address high address low address low data data note: 1 = echo delay (2 bit times) 3 = cancel command delay (11 bit times) 4 = wait 1 bit time before sending next byte. 11 4 11 4 4 4 3, 4 8-mon08sp_1p f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mon functional description MC68HC708XL36 motorola mon 165 a brief description of each monitor mode command follows: table 3. read (read memory) command description read byte from memory operand 2-byte address in high byte:low byte order data returned returns contents of speci?ed address opcode $4a command sequence table 4. write (write memory) command description write byte to memory operand 2-byte address in high byte:low byte order; low byte followed by data byte data returned none opcode $49 command sequence read read echo sent to monitor address high address high address low address low data return write write echo from host address high address high address low address low data data 9-mon08sp_1p f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mon MC68HC708XL36 166 mon motorola table 5. iread (indexed read) command description read next 2 bytes in memory from last address accessed operand 2-byte address in high byte:low byte order data returned returns contents of next two addresses opcode $1a command sequence table 6. iwrite (indexed write) command description write to last address accessed + 1 operand single data byte data returned none opcode $19 command sequence iread iread echo from host data return data iwrite iwrite echo from host data data 10-mon08sp_1p f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mon functional description MC68HC708XL36 motorola mon 167 a sequence of iread or iwrite commands can access a block of memory sequentially over the full 64-kbyte memory map. table 7. readsp (read stack pointer) command description reads stack pointer operand none data returned returns incremented stack pointer value (sp + 1) in high byte:low byte order. opcode $0c command sequence table 8. run (run user program) command description executes pulh and rti instructions operand none data returned none opcode $28 command sequence readsp readsp echo from host sp return sp high low run run echo from host 11-mon08sp_1p f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mon MC68HC708XL36 168 mon motorola the mcu executes the swi and pshh instructions when it enters monitor mode. the run command tells the mcu to execute the pulh and rti instructions. before sending the run command, the host can modify the stacked cpu registers to prepare to run the host program. the readsp command returns the incremented stack pointer value, sp + 1. the high and low bytes of the program counter are at addresses sp + 5 and sp + 6. figure 6. stack pointer at monitor mode entry condition code register accumulator low byte of index register high byte of program counter low byte of program counter sp + 1 sp + 2 sp + 3 sp + 4 sp + 5 sp sp + 6 high byte of index register sp + 7 12-mon08sp_1p f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mon security MC68HC708XL36 motorola mon 169 security a security feature discourages unauthorized reading of eprom locations while in monitor mode. the host can bypass the security feature at monitor mode entry by sending eight security bytes that match the bytes at locations $fff6C$fffd. locations $fff6C$fffd contain user-defined data. note: do not leave locations $fff6C$fffd blank. for security reasons, program locations $fff6C$fffd even if they are not used for vectors. during monitor mode entry, the mcu waits after the power-on reset for the host to send the eight security bytes on pin pa0. figure 7. monitor mode entry timing byte 1 byte 1 echo byte 2 byte 2 echo byte 8 byte 8 echo command command echo p a0 p a7 r st v dd 4096 + 32 cgmxclk cycles 24 cgmxclk cycles 256 cgmxclk cycles (one bit time) 1 4 1 1 2 1 break note: 1 = echo delay (2 bit times) 2 = data return delay (2 bit times) 4 = wait 1 bit time before sending next byte. 4 from host from mcu 13-mon08sp_1p f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . mon MC68HC708XL36 170 mon motorola if the received bytes match those at locations $fff6C$fffd, the host bypasses the security feature and can read all eprom locations and execute code from eprom. security remains bypassed until a power-on reset occurs. after the host bypasses security, any reset other than a power-on reset requires the host to send another eight bytes. if the reset was not a power-on reset, security remains bypassed regardless of the data that the host sends. if the received bytes do not match the data at locations $fff6C$fffd, the host fails to bypass the security feature. the mcu remains in monitor mode, but reading eprom locations returns undefined data, and trying to execute code from eprom causes an illegal address reset. after the host fails to bypass security, any reset other than a power-on reset causes an endless loop of illegal address resets. after receiving the eight security bytes from the host, the mcu transmits a break character signalling that it is ready to receive a command. note: the mcu does not transmit a break character until after the host sends the eight security bytes. 14-mon08sp_1p f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC708XL36 motorola tim 171 timer interface module tim contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .172 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .173 tim counter prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 input capture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 unbuffered output compare. . . . . . . . . . . . . . . . . . . . . . . . . . . . .177 buffered output compare . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .178 pulse width modulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .179 unbuffered pwm signal generation. . . . . . . . . . . . . . . . . . . . . . .180 buffered pwm signal generation . . . . . . . . . . . . . . . . . . . . . . . . .181 pwm initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .182 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .183 low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184 stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .184 tim during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .185 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186 tim clock pin (tclk) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .186 tim channel i/o pins (tch0Ctch3) . . . . . . . . . . . . . . . . . . . . . .186 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .187 tim status and control register. . . . . . . . . . . . . . . . . . . . . . . . . .188 tim dma select register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .190 tim counter registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .191 tim counter modulo registers . . . . . . . . . . . . . . . . . . . . . . . . . . .192 tim channel status and control registers. . . . . . . . . . . . . . . . . .192 1-tim4_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . tim MC68HC708XL36 172 tim motorola tim channel 0 status and control register . . . . . . . . . . . . . . .193 tim channel 1 status and control register . . . . . . . . . . . . . . .193 tim channel 2 status and control register . . . . . . . . . . . . . . .193 tim channel 3 status and control register . . . . . . . . . . . . . . .194 tim channel registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .199 introduction the tim is a 4-channel timer that provides a timing reference with input capture, output compare, and pulse-width-modulation functions. figure 1 is a block diagram of the tim. features features of the tim include the following: ? four input capture/output compare channels C rising-edge, falling-edge, or any-edge input capture trigger C set, clear, or toggle output compare action ? buffered and unbuffered pulse width modulation (pwm) signal generation ? programmable tim clock input C 7-frequency internal bus clock prescaler selection C external tim clock input (4-mhz maximum frequency) ? free-running or modulo up-count operation ? toggle any channel pin on overflow ? tim counter stop and reset bits ? dma service request generation ? modular architecture expandable to eight channels 2-tim4_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . tim pin name conventions MC68HC708XL36 motorola tim 173 pin name conventions the generic names of the tim i/o pins are: ? tclk (tim external clock input pin) ? tch0 (tim channel 0 i/o pin) ? tch1 (tim channel 1 i/o pin) ? tch2 (tim channel 2 i/o pin) ? tch3 (tim channel 3 i/o pin) tim pins are shared by parallel i/o ports. the full name of a tim pin reflects the name of the shared port pin. the generic pin names appear in the text that follows. table 1 shows the full names of the tim i/o pins. functional description figure 1 shows the structure of the tim. the central component of the tim is the 16-bit tim counter that can operate as a free-running counter or a modulo up-counter. the tim counter provides the timing reference for the input capture and output compare functions. the tim counter modulo registers, tmodh:tmodl, control the modulo value of the tim counter. software can read the tim counter value at any time without affecting the counting sequence. the four tim channels are programmable independently as input capture or output compare channels. table 1. pin name conventions generic pin names tclk tch0 tch1 tch2 tch3 full pin names pe3/tclk pe4/tch0 pe5/tch1 pe6/tch2 pe7/tch3 3-tim4_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . tim MC68HC708XL36 174 tim motorola figure 1. tim block diagram prescaler prescaler select internal 16-bit comparator ps2 ps1 ps0 16-bit comparator 16-bit latch tch0h:tch0l ms0a els0b els0a port tof toie inter- 16-bit comparator 16-bit latch tch1h:tch1l 16-bit comparator 16-bit latch tch2h:tch2l 16-bit comparator 16-bit latch tch3h:tch3l channel 0 channel 1 channel 2 channel 3 tmodh:tmodl trst tstop tov0 ch0ie dma0s ch0f els1b els1a tov1 ch1ie dma1s ch1max ch1f els2b els2a tov2 ch2ie dma2s ch2max ch2f els3b els3a tov3 ch3ie dma3s ch3max ch3f ch0max ms0b ms2b 16-bit counter internal bus bus clock ms1a ms2a ms3a logic rupt logic inter- rupt logic port logic inter- rupt logic port logic inter- rupt logic port logic inter- rupt logic tch1 tch2 tch0 tch3 tclk 4-tim4_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . tim functional description MC68HC708XL36 motorola tim 175 register name bit 7 654321 bit 0 tim status and control register (tsc) read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset: 00100000 tim dma select register (tdma) read: 0000 dma3s dma2s dma1s dma0s write: reset: 00000000 tim counter register high (tcnth) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 00000000 tim counter register low (tcntl read: bit 7 654321 bit 0 write: reset: 00000000 tim counter modulo register high (tmodh) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 11111111 tim counter modulo register low (tmodl) read: bit 7 654321 bit 0 write: reset: 11111111 tim channel 0 status and control register (tsc0) read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset: 00000000 tim channel 0 register high (tch0h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset tim channel 0 register low (tch0l) read: bit 7 654321 bit 0 write: reset: indeterminate after reset tim channel 1 status and control register (tsc1) read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset: 00000000 tim channel 1 register high (tch1h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset tim channel 1 register low (tch1l) read: bit 7 654321 bit 0 write: reset: indeterminate after reset tim channel 2 status and control register (tsc2) read: ch2f ch2ie ms2b ms2a els2b els2a tov2 ch2max write: 0 reset: 00000000 tim channel 2 register high (tch2h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset = unimplemented figure 2. i/o register summary 5-tim4_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . tim MC68HC708XL36 176 tim motorola tim channel 2 register low (tch2l) read: bit 7 654321 bit 0 write: reset: indeterminate after reset tim channel 3 status and control register (tsc3) read: ch3f ch3ie 0 ms3a els3b els3a tov3 ch3max write: 0 reset: 00000000 tim channel 3 register high (tch3h) read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset tim channel 3 register low (tch3l) read: bit 7 654321 bit 0 write: reset: indeterminate after reset table 2. i/o register address summary register tsc tdma tcnth tcntl tmodh tmodl tsc0 tch0h tch0l tsc1 address $0020 $0021 $0022 $0023 $0024 $0025 $0026 $0027 $0028 $0029 register tch1h tch1l tsc2 tch2h tch2l tsc3 tch3h tch3l address $002a $002b $002c $002d $002e $002f $0030 $0031 register name bit 7 654321 bit 0 = unimplemented figure 2. i/o register summary 6-tim4_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . tim functional description MC68HC708XL36 motorola tim 177 tim counter prescaler the tim clock source can be one of the seven prescaler outputs or the tim clock pin, tclk. the prescaler generates seven clock rates from the internal bus clock. the prescaler select bits, ps[2:0], in the tim status and control register select the tim clock source. input capture with the input capture function, the tim can capture the time at which an external event occurs. when an active edge occurs on the pin of an input capture channel, the tim latches the contents of the tim counter into the tim channel registers, tchxh:tchxl. the polarity of the active edge is programmable. input capture latency can be up to three bus clock cycles. input captures can generate tim cpu interrupt requests or tim dma service requests. output compare with the output compare function, the tim can generate a periodic pulse with a programmable polarity, duration, and frequency. when the counter reaches the value in the registers of an output compare channel, the tim can set, clear, or toggle the channel pin. output compares can generate tim cpu interrupt requests or tim dma service requests. unbuffered output compare any output compare channel can generate unbuffered output compare pulses as described in output compare . the pulses are unbuffered because changing the output compare value requires writing the new value over the old value currently in the tim channel registers. an unsynchronized write to the tim channel registers to change an output compare value could cause incorrect operation for up to two counter overflow periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that counter overflow period. also, using a tim overflow interrupt routine to write a new, smaller output compare value may cause the compare to be missed. the tim may pass the new value before it is written. 7-tim4_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . tim MC68HC708XL36 178 tim motorola use the following methods to synchronize unbuffered changes in the output compare value on channel x: ? when changing to a smaller value, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current output compare pulse. the interrupt routine has until the end of the counter overflow period to write the new value. ? when changing to a larger output compare value, enable channel x tim overflow interrupts and write the new value in the tim overflow interrupt routine. the tim overflow interrupt occurs at the end of the current counter overflow period. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same counter overflow period. buffered output compare channels 0 and 1 can be linked to form a buffered output compare channel whose output appears on the tch0 pin. the tim channel registers of the linked pair alternately control the output. setting the ms0b bit in tim channel 0 status and control register (tsc0) links channel 0 and channel 1. the output compare value in the tim channel 0 registers initially controls the output on the tch0 pin. writing to the tim channel 1 registers enables the tim channel 1 registers to synchronously control the output after the tim overflows. at each subsequent overflow, the tim channel registers (0 or 1) that control the output are the ones written to last. tsc0 controls and monitors the buffered output compare function, and tim channel 1 status and control register (tsc1) is unused. while the ms0b bit is set, the channel 1 pin, tch1, is available as a general-purpose i/o pin. channels 2 and 3 can be linked to form a buffered output compare channel whose output appears on the tch2 pin. the tim channel registers of the linked pair alternately control the output. setting the ms2b bit in tim channel 2 status and control register (tsc2) links channel 2 and channel 3. the output compare value in the tim channel 2 registers initially controls the output on the tch2 pin. writing 8-tim4_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . tim functional description MC68HC708XL36 motorola tim 179 to the tim channel 3 registers enables the tim channel 3 registers to synchronously control the output after the tim overflows. at each subsequent overflow, the tim channel registers (2 or 3) that control the output are the ones written to last. tsc2 controls and monitors the buffered output compare function, and tim channel 3 status and control register (tsc3) is unused. while the ms2b bit is set, the channel 3 pin, tch3, is available as a general-purpose i/o pin. note: in buffered output compare operation, do not write new output compare values to the currently active channel registers. writing to the active channel registers is the same as generating unbuffered output compares. pulse width modulation by using the toggle-on-overflow feature with an output compare channel, the tim can generate a pwm signal. the value in the tim counter modulo registers determines the period of the pwm signal. the channel pin toggles when the counter reaches the value in the tim counter modulo registers. the time between overflows is the period of the pwm signal. as figure 3 shows, the output compare value in the tim channel registers determines the pulse width of the pwm signal. the time between overflow and output compare is the pulse width. program the tim to clear the channel pin on output compare if the state of the pwm pulse is logic 1. program the tim to set the pin if the state of the pwm pulse is logic 0. figure 3. pwm period and pulse width tchx period pulse width overflow overflow overflow output compare output compare output compare 9-tim4_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . tim MC68HC708XL36 180 tim motorola the value in the tim counter modulo registers and the selected prescaler output determines the frequency of the pwm output. the frequency of an 8-bit pwm signal is variable in 256 increments. writing $00ff (255) to the tim counter modulo registers produces a pwm period of 256 times the internal bus clock period if the prescaler select value is $000. see tim status and control register on page 188. the value in the tim channel registers determines the pulse width of the pwm output. the pulse width of an 8-bit pwm signal is variable in 256 increments. writing $0080 (128) to the tim channel registers produces a duty cycle of 128/256 or 50%. unbuffered pwm signal generation any output compare channel can generate unbuffered pwm pulses as described in pulse width modulation on page 179. the pulses are unbuffered because changing the pulse width requires writing the new pulse width value over the old value currently in the tim channel registers. an unsynchronized write to the tim channel registers to change a pulse width value could cause incorrect operation for up to two pwm periods. for example, writing a new value before the counter reaches the old value but after the counter reaches the new value prevents any compare during that pwm period. also, using a tim overflow interrupt routine to write a new, smaller pulse width value may cause the compare to be missed. the tim may pass the new value before it is written. use the following methods to synchronize unbuffered changes in the pwm pulse width on channel x: ? when changing to a shorter pulse width, enable channel x output compare interrupts and write the new value in the output compare interrupt routine. the output compare interrupt occurs at the end of the current pulse. the interrupt routine has until the end of the pwm period to write the new value. ? when changing to a longer pulse width, enable channel x tim overflow interrupts and write the new value in the tim overflow interrupt routine. the tim overflow interrupt occurs at the end of 10-tim4_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . tim functional description MC68HC708XL36 motorola tim 181 the current pwm period. writing a larger value in an output compare interrupt routine (at the end of the current pulse) could cause two output compares to occur in the same pwm period. note: in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. toggling on output compare also can cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. buffered pwm signal generation channels 0 and 1 can be linked to form a buffered pwm channel whose output appears on the tch0 pin. the tim channel registers of the linked pair alternately control the pulse width of the output. setting the ms0b bit in tim channel 0 status and control register (tsc0) links channel 0 and channel 1. the tim channel 0 registers initially control the pulse width on the tch0 pin. writing to the tim channel 1 registers enables the tim channel 1 registers to synchronously control the pulse width at the beginning of the next pwm period. at each subsequent overflow, the tim channel registers (0 or 1) that control the pulse width are the ones written to last. tsc0 controls and monitors the buffered pwm function, and tim channel 1 status and control register (tsc1) is unused. while the ms0b bit is set, the channel 1 pin, tch1, is available as a general-purpose i/o pin. channels 2 and 3 can be linked to form a buffered pwm channel whose output appears on the tch2 pin. the tim channel registers of the linked pair alternately control the pulse width of the output. setting the ms2b bit in tim channel 2 status and control register (tsc2) links channel 2 and channel 3. the tim channel 2 registers initially control the pulse width on the tch2 pin. writing to the tim channel 3 registers enables the tim channel 3 registers to synchronously control the pulse width at the beginning of the next pwm period. at each subsequent overflow, the tim channel registers (2 or 3) that control the pulse width are the ones written to last. tsc2 controls and monitors the buffered pwm function, and tim channel 3 status and control register (tsc3) is unused. while the ms2b bit is set, the channel 3 pin, tch3, is available as a general-purpose i/o pin. 11-tim4_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . tim MC68HC708XL36 182 tim motorola note: in buffered pwm signal generation, do not write new pulse width values to the currently active channel registers. writing to the active channel registers is the same as generating unbuffered pwm signals. pwm initialization to ensure correct operation when generating unbuffered or buffered pwm signals, use the following initialization procedure: 1. in the tim status and control register (tsc): a. stop the tim counter by setting the tim stop bit, tstop. b. reset the tim counter by setting the tim reset bit, trst. 2. in the tim counter modulo registers (tmodh:tmodl), write the value for the required pwm period. 3. in the tim channel x registers (tchxh:tchxl), write the value for the required pulse width. 4. in tim channel x status and control register (tscx): a. write 0:1 (for unbuffered output compare or pwm signals) or 1:0 (for buffered output compare or pwm signals) to the mode select bits, msxb:msxa. see table 4 on page 197. b. write 1 to the toggle-on-overflow bit, tovx. c. write 1:0 (to clear output on compare) or 1:1 (to set output on compare) to the edge/level select bits, elsxb:elsxa. the output action on compare must force the output to the complement of the pulse width level. see table 4 on page 197. note: in pwm signal generation, do not program the pwm channel to toggle on output compare. toggling on output compare prevents reliable 0% duty cycle generation and removes the ability of the channel to self-correct in the event of software error or noise. toggling on output compare can also cause incorrect pwm signal generation when changing the pwm pulse width to a new, much larger value. 5. in the tim status control register (tsc), clear the tim stop bit, tstop. 12-tim4_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . tim interrupts MC68HC708XL36 motorola tim 183 setting ms0b links channels 0 and 1 and configures them for buffered pwm operation. the tim channel 0 registers (tch0h:tch0l) initially control the buffered pwm output. tim status control register 0 (tscr0) controls and monitors the pwm signal from the linked channels. ms0b takes priority over ms0a. setting ms2b links channels 2 and 3 and configures them for buffered pwm operation. the tim channel 2 registers (tch2h:tch2l) initially control the pwm output. tim status control register 2 (tscr2) controls and monitors the pwm signal from the linked channels. ms2b takes priority over ms2a. clearing the toggle-on-overflow bit, tovx, inhibits output toggles on tim overflows. subsequent output compares try to force the output to a state it is already in and have no effect. the result is a 0% duty cycle output. setting the channel x maximum duty cycle bit (chxmax) and clearing the tovx bit generates a 100% duty cycle output. see tim channel status and control registers on page 192. interrupts the following tim sources can generate interrupt requests: ? tim overflow flag (tof) the tof bit is set when the tim counter value rolls over to $0000 after matching the value in the tim counter modulo registers. the tim overflow interrupt enable bit, toie, enables tim overflow cpu interrupt requests. tof and toie are in the tim status and control register. ? tim channel flags (ch3fCch0f) the chxf bit is set when an input capture or output compare occurs on channel x. channel x tim cpu interrupt requests and tim dma service requests are controlled by the channel x interrupt enable bit, chxie, and the channel x dma select bit, dmaxs. channel x tim cpu interrupt requests are enabled when chxie:dmaxs = 1:0. channel x tim dma service requests are enabled when chxie:dmaxs = 1:1. chxf and chxie are in the tim channel x status and control register. dmaxs is in the tim dma select register. 13-tim4_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . tim MC68HC708XL36 184 tim motorola low-power modes the wait and stop instructions put the mcu in low-power-consump- tion standby modes. wait mode the tim remains active in wait mode. any enabled cpu interrupt request from the tim can bring the mcu out of wait mode. if tim functions are not required during wait mode, reduce power consumption by stopping the tim before executing the wait instruction. the dma can service the tim without exiting wait mode. stop mode the tim is inactive in stop mode. the stop instruction does not affect register states or the state of the tim counter. tim operation resumes when the mcu exits stop mode after an external interrupt. 14-tim4_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . tim tim during break interrupts MC68HC708XL36 motorola tim 185 tim during break interrupts a break interrupt stops the tim counter. the bcfe bit in the break flag control register (bfcr) enables software to clear status bits during the break state. see break module on page 149. to allow software to clear status bits during a break interrupt, write a logic 1 to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break state, write a logic 0 to the bcfe bit. with bcfe at logic 0 (its default state), software can read and write i/o registers during the break state without affecting status bits. some status bits have a two-step read/write clearing procedure. if software does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is at logic 0. after the break, doing the second step clears the status bit. 15-tim4_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . tim MC68HC708XL36 186 tim motorola i/o signals port e shares five of its pins with the tim. tclk is an external clock input to the tim prescaler. the four tim channel i/o pins are tch0, tch1, tch2, and tch3. tim clock pin (tclk) tclk is an external clock input that can be the clock source for the tim counter instead of the prescaled internal bus clock. select the tclk input by writing logic 1s to the three prescaler select bits, ps[2:0]. see tim status and control register on page 188. the minimum tclk pulse width, tclk lmin or tclk hmin , is: the maximum tclk frequency is: bus frequency ? 2 tclk is available as a general-purpose i/o pin when not used as the tim clock input. when the tclk pin is the tim clock input, it is an input regardless of the state of the ddre3 bit in data direction register e. tim channel i/o pins (tch0Ctch3) each channel i/o pin is programmable independently as an input capture pin or an output compare pin. tch0 and tch2 can be configured as buffered output compare or buffered pwm pins. 1 bus frequency ------------------------------------- t su + 16-tim4_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . tim i/o registers MC68HC708XL36 motorola tim 187 i/o registers these i/o registers control and monitor operation of the tim: ? tim status and control register (tsc) ? tim dma select register (tdma) ? tim control registers (tcnth:tcntl) ? tim counter modulo registers (tmodh:tmodl) ? tim channel status and control registers (tsc0, tsc1, tsc2, and tsc3) ? tim channel registers (tch0h:tch0l, tch1h:tch1l, tch2h:tch2l, and tch3h:tch3l) 17-tim4_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . tim MC68HC708XL36 188 tim motorola tim status and control register the tim status and control register: ? enables tim overflow interrupts ? flags tim overflows ? stops the tim counter ? resets the tim counter ? prescales the tim counter clock tof tim overflow flag bit this read/write flag is set when the tim counter resets to $0000 after reaching the modulo value programmed in the tim counter modulo registers. clear tof by reading the tim status and control register when tof is set and then writing a logic 0 to tof. if another tim overflow occurs before the clearing sequence is complete, then writing logic 0 to tof has no effect. therefore, a tof interrupt request cannot be lost due to inadvertent clearing of tof. reset clears the tof bit. writing a logic 1 to tof has no effect. 1 = modulo value reached 0 = modulo value not reached toie tim overflow interrupt enable bit this read/write bit enables tim overflow interrupts when the tof bit becomes set. reset clears the toie bit. 1 = tim overflow interrupts enabled 0 = tim overflow interrupts disabled address: $0020 bit 7 654321 bit 0 read: tof toie tstop 00 ps2 ps1 ps0 write: 0 trst reset: 00100000 = unimplemented figure 4. tim status and control register (tsc) 18-tim4_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . tim i/o registers MC68HC708XL36 motorola tim 189 tstop tim stop bit this read/write bit stops the tim counter. counting resumes when tstop is cleared. reset sets the tstop bit, stopping the tim counter until software clears the tstop bit. 1 = tim counter stopped 0 = tim counter active note: do not set the tstop bit before entering wait mode if the tim is required to exit wait mode. trst tim reset bit setting this write-only bit resets the tim counter and the tim prescaler. setting trst has no effect on any other registers. counting resumes from $0000. trst is cleared automatically after the tim counter is reset and always reads as logic 0. reset clears the trst bit. 1 = prescaler and tim counter cleared 0 = no effect note: setting the tstop and trst bits simultaneously stops the tim counter at a value of $0000. ps[2:0] prescaler select bits these read/write bits select either the tclk pin or one of the seven prescaler outputs as the input to the tim counter as table 3 shows. reset clears the ps[2:0] bits. table 3. prescaler selection ps[2:0] tim clock source 000 internal bus clock 001 internal bus clock ? 2 010 internal bus clock ? 4 011 internal bus clock ? 8 100 internal bus clock ? 16 101 internal bus clock ? 32 110 internal bus clock ? 64 111 tclk 19-tim4_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . tim MC68HC708XL36 190 tim motorola tim dma select register the tim dma select register enables either tim cpu interrupt requests or tim dma service requests. dma3s dma channel 3 select bit this read/write bit enables tim dma service requests on channel 3. reset clears the dma3s bit. 1 = tim dma service requests enabled on channel 3 tim cpu interrupt requests disabled on channel 3 0 = tim dma service requests disabled on channel 3 tim cpu interrupt requests enabled on channel 3 dma2s dma channel 2 select bit this read/write bit enables tim dma service requests on channel 2. reset clears the dma2s bit. 1 = tim dma service requests enabled on channel 2 tim cpu interrupt requests disabled on channel 2 0 = tim dma service requests disabled on channel 2 tim cpu interrupt requests enabled on channel 2 dma1s dma channel 1 select bit this read/write bit enables tim dma service requests on channel 1. reset clears the dma1s bit. 1 = tim dma service requests enabled on channel 1 tim cpu interrupt requests disabled on channel 1 0 = tim dma service requests disabled on channel 1 tim cpu interrupt requests enabled on channel 1 address: $0021 bit 7 654321 bit 0 read: 0000 dma3s dma2s dma1s dma0s write: reset: 00000000 = unimplemented figure 5. tim dma select register (tdma) 20-tim4_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . tim i/o registers MC68HC708XL36 motorola tim 191 dma0s dma channel 0 select bit this read/write bit enables tim dma service requests on channel 0. reset clears the dma0s bit. 1 = tim dma service requests enabled on channel 0 tim cpu interrupt requests disabled on channel 0 0 = tim dma service requests disabled on channel 0 tim cpu interrupt requests enabled on channel 0 tim counter registers the two read-only tim counter registers contain the high and low bytes of the value in the tim counter. reading the high byte (tcnth) latches the contents of the low byte (tcntl) into a buffer. subsequent reads of tcnth do not affect the latched tcntl value until tcntl is read. reset clears the tim counter registers. setting the tim reset bit (trst) also clears the tim counter registers. note: if you read tcnth during a break interrupt, be sure to unlatch tcntl by reading tcntl before exiting the break interrupt. otherwise, tcntl retains the value latched during the break. address: $0022 : $0023 bit 7 654321 bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 00000000 bit 7 654321 bit 0 read: bit 7 654321 bit 0 write: reset: 00000000 = unimplemented figure 6. tim counter registers (tcnth:tcntl) 21-tim4_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . tim MC68HC708XL36 192 tim motorola tim counter modulo registers the read/write tim modulo registers contain the modulo value for the tim counter. when the tim counter reaches the modulo value, the overflow flag (tof) becomes set, and the tim counter resumes counting from $0000 at the next clock. writing to the high byte (tmodh) inhibits the tof bit and overflow interrupts until the low byte (tmodl) is written. reset sets the tim counter modulo registers. note: reset the tim counter before writing to the tim counter modulo registers. tim channel status and control registers each of the tim channel status and control registers: ? flags input captures and output compares. ? enables input capture and output compare interrupts. ? selects input capture, output compare, or pwm operation. ? selects high, low, or toggling output on output compare. ? selects rising, falling, or any edge as the input capture trigger. ? selects output toggling on tim overflow. ? selects 100% pwm duty cycle. ? selects buffered or unbuffered output compare/pwm operation. address: $0024 : $0025 bit 7 654321 bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: 11111111 bit 7 654321 bit 0 read: bit 7 654321 bit 0 write: reset: 11111111 figure 7. tim counter modulo registers (tmodh:tmodl) 22-tim4_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . tim i/o registers MC68HC708XL36 motorola tim 193 tim channel 0 status and control register tim channel 1 status and control register tim channel 2 status and control register address: $0026 bit 7 654321 bit 0 read: ch0f ch0ie ms0b ms0a els0b els0a tov0 ch0max write: 0 reset: 00000000 figure 8. tim channel 0 status and control register (tsc0) address: $0029 bit 7 654321 bit 0 read: ch1f ch1ie 0 ms1a els1b els1a tov1 ch1max write: 0 reset: 00000000 = unimplemented figure 9. tim channel 1 status and control register (tsc1) address: $002c bit 7 654321 bit 0 read: ch2f ch2ie ms2b ms2a els2b els2a tov2 ch2max write: 0 reset: 00000000 figure 10. tim channel 2 status and control register (tsc2) 23-tim4_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . tim MC68HC708XL36 194 tim motorola tim channel 3 status and control register chxf channel x flag bit when channel x is an input capture channel, this read/write bit is set when an active edge occurs on the channel x pin. when channel x is an output compare channel, chxf is set when the value in the tim counter registers matches the value in the tim channel x registers. when tim cpu interrupt requests are enabled (chxie:dmaxs = 1:0), clear chxf by reading tim channel x status and control register with chxf set and then writing a logic 0 to chxf. if another interrupt request occurs before the clearing sequence is complete, then writing logic 0 to chxf has no effect. therefore, an interrupt request cannot be lost due to inadvertent clearing of chxf. when tim dma service requests are enabled (chxie:dmaxs = 1:1), clear chxf by reading or writing to the low byte of the tim channel x registers (tchxl). reset clears the chxf bit. writing a logic 1 to chxf has no effect. 1 = input capture or output compare on channel x 0 = no input capture or output compare on channel x note: reading the high byte of the timer channel x registers (tchxh) inhibits the chxf bit until the low byte (tchxl) is read. address: $002f bit 7 654321 bit 0 read: ch3f ch3ie 0 ms3a els3b els3a tov3 ch3max write: 0 reset: 00000000 = unimplemented figure 11. tim channel 3 status and control register (tsc3) 24-tim4_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . tim i/o registers MC68HC708XL36 motorola tim 195 chxie channel x interrupt enable bit this read/write bit enables tim cpu interrupts and tim dma service requests on channel x. the dmaxs bit in the tim dma select register selects channel x tim dma service requests or tim cpu interrupt requests. note: tim dma service requests cannot be used in buffered pwm mode. in buffered pwm mode, disable tim dma service requests by clearing the dmaxs bit in the tim dma select register. reset clears the chxie bit. 1 = channel x cpu interrupt requests and dma service requests enabled 0 = channel x cpu interrupt requests and dma service requests disabled msxb mode select bit b this read/write bit selects buffered output compare/pwm operation. msxb exists only in the tim channel 0 and tim channel 2 status and control registers. setting ms0b disables the channel 1 status and control register and reverts tch1 to general-purpose i/o. setting ms2b disables the channel 3 status and control register and reverts tch3 to general-purpose i/o. reset clears the msxb bit. 1 = buffered output compare/pwm operation enabled 0 = buffered output compare/pwm operation disabled 25-tim4_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . tim MC68HC708XL36 196 tim motorola msxa mode select bit a when elsxb:a 1 00, this read/write bit selects either input capture operation or unbuffered output compare/pwm operation. see table 4 . 1 = unbuffered output compare/pwm operation 0 = input capture operation when elsxb:a = 00, this read/write bit selects the initial output level of the tchx pin. see table 4 . reset clears the msxa bit. 1 = initial output level low 0 = initial output level high note: before changing a channel function by writing to the msxb or msxa bit, set the tstop and trst bits in the tim status and control register (tsc). 26-tim4_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . tim i/o registers MC68HC708XL36 motorola tim 197 elsxb and elsxa edge/level select bits when channel x is an input capture channel, these read/write bits control the active edge-sensing logic on channel x. when channel x is an output compare channel, elsxb and elsxa control the channel x output behavior when an output compare occurs. when elsxb and elsxa are both clear, channel x is not connected to port e, and pin tchx is available as a general-purpose i/o pin. table 4 shows how elsxb and elsxa work. reset clears the elsxb and elsxa bits. note: before enabling a tim channel register for input capture operation, make sure that the chx pin is stable for at least two bus clocks. table 4. mode, edge, and level selection msx[b:a] elsx[b:a] mode configuration x0 00 output preset pin under port control; initial output level high x1 00 pin under port control; initial output level low 00 01 input capture capture on rising edge only 00 10 capture on falling edge only 00 11 capture on rising or falling edge 01 01 output compare or pwm toggle output on compare 01 10 clear output on compare 01 11 set output on compare 1x 01 buffered output compare or buffered pwm toggle output on compare 1x 10 clear output on compare 1x 11 set output on compare 27-tim4_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . tim MC68HC708XL36 198 tim motorola tovx toggle-on-overflow bit when channel x is an output compare channel, this read/write bit controls the behavior of the channel x output when the tim counter overflows. when channel x is an input capture channel, tovx has no effect. reset clears the tovx bit. 1 = channel x pin toggles on tim counter overflow. 0 = channel x pin does not toggle on tim counter overflow. note: when tovx is set, a tim counter overflow takes precedence over a channel x output compare if both occur at the same time. note: reading the high byte of the timer channel x registers (tchxh) prevents the channel x pin from toggling until the low byte (tchxl) is read. chxmax channel x maximum duty cycle bit when the tovx bit is at logic 0, setting the chxmax bit forces the duty cycle of buffered and unbuffered pwm signals to 100%. as figure 12 shows, the chxmax bit takes effect in the cycle after it is set or cleared. the output stays at the 100% duty cycle level until the cycle after chxmax is cleared. figure 12. chxmax latency period output compare output compare output compare output compare overflow overflow overflow overflow overflow tchx chxmax 28-tim4_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . tim i/o registers MC68HC708XL36 motorola tim 199 tim channel registers these read/write registers contain the captured tim counter value of the input capture function or the output compare value of the output compare function. the state of the tim channel registers after reset is unknown. in input capture mode, reading tchxh prevents the input capture value from latching into the channel registers and inhibits the chxf bit until tchxl is read. in output compare mode, writing to tchxh prevents the channel x pin from toggling and inhibits the chxf bit until tchxl is written. bit 7 654321 bit 0 read: bit 15 14 13 12 11 10 9 bit 8 write: reset: indeterminate after reset read: bit 7 654321 bit 0 write: reset: indeterminate after reset figure 13. tim channel registers (tch0h/lCtch3h/l) table 5. tim channel register address summary register tch0h tch0l tch1h tch1l tch2h tch2l tch3h tch3l address $0027 $0028 $002a $002b $002d $002e $0030 $0031 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . tim MC68HC708XL36 200 tim motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC708XL36 motorola spi 201 serial peripheral interface module spi contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .202 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .203 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .204 master mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .205 slave mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .207 transmission formats . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .208 clock phase and polarity controls . . . . . . . . . . . . . . . . . . . . . . . .208 transmission format when cpha = 0 . . . . . . . . . . . . . . . . . . . . .208 transmission format when cpha = 1 . . . . . . . . . . . . . . . . . . . . .210 transmission initiation latency. . . . . . . . . . . . . . . . . . . . . . . . . . .211 queuing transmission data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .213 error conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214 overflow error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .214 mode fault error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .218 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .221 resetting the spi. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .222 low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .223 stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224 spi during break interrupts. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .224 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225 miso (master in/slave out) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .225 mosi (master out/slave in) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226 spsck (serial clock) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226 ss (slave select) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .226 cgnd (clock ground) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .227 1-spi_c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . spi MC68HC708XL36 202 spi motorola i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228 spi control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .228 spi status and control register . . . . . . . . . . . . . . . . . . . . . . . . . .230 spi data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .234 introduction the spi allows full-duplex, synchronous, serial communications with peripheral devices. features features of the spi module include the following: ? full-duplex operation ? master and slave modes ? double-buffered operation with separate transmit and receive registers ? four master mode frequencies (maximum = bus frequency ? 2) ? maximum slave mode frequency = bus frequency ? clock ground for reduced radio frequency (rf) interference ? serial clock with programmable polarity and phase ? two separately enabled interrupts with dma or cpu service: C sprf (spi receiver full) C spte (spi transmitter empty) ? mode fault error flag with cpu interrupt capability ? overflow error flag with cpu interrupt capability ? programmable wired-or mode ? limited i 2 c (inter-integrated circuit) compatibility 2-spi_c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . spi pin name conventions MC68HC708XL36 motorola spi 203 pin name conventions the generic names of the spi i/o pins are: ? ss (slave select) ? spsck (spi serial clock) ? cgnd (clock ground) ? mosi (master out slave in) ? miso (master in slave out) spi pins are shared by parallel i/o ports or have alternate functions. the full name of an spi pin reflects the name of the shared port pin or the name of an alternate pin function. the generic pin names appear in the text that follows. table 1 shows the full names of the spi i/o pins. table 1. pin name conventions generic pin names miso mosi ss spsck cgnd full pin names pf3/miso pf2/mosi pf0/ ss pf1/spsck cgnd/ev ss 3-spi_c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . spi MC68HC708XL36 204 spi motorola functional description figure 1 shows the structure of the spi module and figure 2 shows the locations and contents of the spi i/o registers. figure 1. spi module block diagram transmitter cpu interrupt request receiver dma service request receiver/error cpu interrupt request 76543210 spr1 spmstr transmit data register shift register spr0 bus clock ? 2 clock select ? 2 clock divider ? 8 ? 32 ? 128 clock logic cpha cpol spi sprie dmas spe spwom sprf spte ovrf transmitter dma service request m s pin control logic receive data register sptie spe internal bus modfen errie control modf spmstr mosi miso spsck ss 4-spi_c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . spi functional description MC68HC708XL36 motorola spi 205 the spi module allows full-duplex, synchronous, serial communication between the mcu and peripheral devices, including other mcus. software can poll the spi status flags or spi operation can be interrupt-driven. all spi interrupts can be serviced by the cpu, and the transmitter empty (spte) and receiver full (sprf) flags can also be configured for dma service. during dma transmissions, the dma fetches data from memory for the spi to transmit and/or the dma stores received data in memory. the following paragraphs describe the operation of the spi module. master mode the spi operates in master mode when the spi master bit, spmstr, is set. note: configure the spi modules as master or slave before enabling them. enable the master spi before enabling the slave spi. disable the slave spi before disabling the master spi. register name bit 7 654321 bit 0 spi control register (spcr) read: sprie dmas spmstr cpol cpha spwom spe sptie write: reset: 00100000 spi status and control register (spscr) read: sprf errie ovrf modf spte modfen spr1 spr0 write: reset: 00001000 spi data register (spdr) read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset = unimplemented figure 2. spi i/o register summary table 2. i/o register address summary register spcr spscr spdr address $0010 $0011 $0012 5-spi_c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . spi MC68HC708XL36 206 spi motorola only a master spi module can initiate transmissions. software begins the transmission from a master spi module by writing to the transmit data register. if the shift register is empty, the byte immediately transfers to the shift register, setting the spi transmitter empty bit, spte. the byte begins shifting out on the mosi pin under the control of the serial clock. (see figure 3 .) the spr1 and spr0 bits control the baud rate generator and determine the speed of the shift register. (see spi status and control register on page 230.) through the spsck pin, the baud rate generator of the master also controls the shift register of the slave peripheral. as the byte shifts out on the mosi pin of the master, another byte shifts in from the slave on the masters miso pin. the transmission ends when the receiver full bit, sprf, becomes set. at the same time that sprf becomes set, the byte from the slave transfers to the receive data register. in normal operation, sprf signals the end of a transmission. software clears sprf by reading the spi status and control register with sprf set and then reading the spi data register. writing to the spi data register clears the spte bit. when the dmas bit is set, the spi status and control register does not have to be read to clear the sprf bit. a read of the spi data register by either the cpu or the dma clears the sprf bit. a write to the spi data register by the cpu or by the dma clears the spte bit. figure 3. full-duplex master-slave connections shift register shift register baud rate generator master mcu slave mcu v dd mosi mosi miso miso spsck spsck ss ss 6-spi_c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . spi functional description MC68HC708XL36 motorola spi 207 slave mode the spi operates in slave mode when the spmstr bit is clear. in slave mode, the spsck pin is the input for the serial clock from the master mcu. before a data transmission occurs, the ss pin of the slave spi must be at logic 0. ss must remain low until the transmission is complete. (see mode fault error on page 218.) in a slave spi module, data enters the shift register under the control of the serial clock from the master spi module. after a byte enters the shift register of a slave spi, it transfers to the receive data register, and the sprf bit is set. to prevent an overflow condition, slave software then must read the receive data register before another full byte enters the shift register. the maximum frequency of the spsck for an spi configured as a slave is the bus clock speed (which is twice as fast as the fastest master spsck clock that can be generated). the frequency of the spsck for an spi configured as a slave does not have to correspond to any spi baud rate. the baud rate only controls the speed of the spsck generated by an spi configured as a master. therefore, the frequency of the spsck for an spi configured as a slave can be any frequency less than or equal to the bus speed. when the master spi starts a transmission, the data in the slave shift register begins shifting out on the miso pin. the slave can load its shift register with a new byte for the next transmission by writing to its transmit data register. the slave must write to its transmit data register at least one bus cycle before the master starts the next transmission. otherwise the byte already in the slave shift register shifts out on the miso pin. data written to the slave shift register during a transmission remains in a buffer until the end of the transmission. when the clock phase bit (cpha) is set, the first edge of spsck starts a transmission. when cpha is clear, the falling edge of ss starts a transmission. (see transmission formats on page 208.) note: spsck must be in the proper idle state before the slave is enabled to prevent spsck from appearing as a clock edge. 7-spi_c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . spi MC68HC708XL36 208 spi motorola transmission formats during an spi transmission, data is simultaneously transmitted (shifted out serially) and received (shifted in serially). a serial clock synchronizes shifting and sampling on the two serial data lines. a slave select line allows selection of an individual slave spi device; slave devices that are not selected do not interfere with spi bus activities. on a master spi device, the slave select line can optionally be used to indicate multiple-master bus contention. clock phase and polarity controls software can select any of four combinations of serial clock (spsck) phase and polarity using two bits in the spi control register (spcr). the clock polarity is specified by the cpol control bit, which selects an active high or low clock and has no significant effect on the transmission format. the clock phase (cpha) control bit selects one of two fundamentally different transmission formats. the clock phase and polarity should be identical for the master spi device and the communicating slave device. in some cases, the phase and polarity are changed between transmissions to allow a master device to communicate with peripheral slaves having different requirements. note: before writing to the cpol bit or the cpha bit, disable the spi by clearing the spi enable bit (spe). transmission format when cpha = 0 figure 4 shows an spi transmission in which cpha is logic 0. the figure should not be used as a replacement for data sheet parametric information.two waveforms are shown for spsck: one for cpol = 0 and another for cpol = 1. the diagram may be interpreted as a master or slave timing diagram since the serial clock (spsck), master in/slave out (miso), and master out/slave in (mosi) pins are directly connected between the master and the slave. the miso signal is the output from the slave, and the mosi signal is the output from the master. the ss line is the slave select input to the slave. the slave spi drives its miso output only when its slave select input ( ss) is at logic 0, so that only the selected slave drives to the master. the ss pin of the master is not 8-spi_c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . spi transmission formats MC68HC708XL36 motorola spi 209 shown but is assumed to be inactive. the ss pin of the master must be high or must be reconfigured as general-purpose i/o not affecting the spi. (see mode fault error on page 218.) when cpha = 0, the first spsck edge is the msb capture strobe. therefore, the slave must begin driving its data before the first spsck edge, and a falling edge on the ss pin is used to start the slave data transmission. the slaves ss pin must be toggled back to high and then low again between each byte transmitted as shown in figure 5 . figure 4. transmission format (cpha = 0) figure 5. cpha/ ss timing when cpha = 0 for a slave, the falling edge of ss indicates the beginning of the transmission. this causes the spi to leave its idle state and begin driving the miso pin with the msb of its data. once the transmission begins, no new data is allowed into the shift register from the transmit data register. therefore, the spi data register of the slave must be loaded with transmit data before the falling edge of ss. any data written after the falling edge is stored in the transmit data register and transferred to the shift register after the current transmission. bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb 12345678 spsck cycle # (for reference) spsck (cpol = 0) spsck (cpol =1) mosi (from master) miso (from slave) ss (to slave) capture strobe byte 1 byte 3 miso/mosi byte 2 master ss slave ss (cpha = 0) slave ss (cpha = 1) 9-spi_c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . spi MC68HC708XL36 210 spi motorola transmission format when cpha = 1 figure 6 shows an spi transmission in which cpha is logic 1. the figure should not be used as a replacement for data sheet parametric information. two waveforms are shown for spsck: one for cpol = 0 and another for cpol = 1. the diagram may be interpreted as a master or slave timing diagram since the serial clock (spsck), master in/slave out (miso), and master out/slave in (mosi) pins are directly connected between the master and the slave. the miso signal is the output from the slave, and the mosi signal is the output from the master. the ss line is the slave select input to the slave. the slave spi drives its miso output only when its slave select input ( ss) is at logic 0, so that only the selected slave drives to the master. the ss pin of the master is not shown but is assumed to be inactive. the ss pin of the master must be high or must be reconfigured as general-purpose i/o not affecting the spi. (see mode fault error on page 218.) when cpha = 1, the master begins driving its mosi pin on the first spsck edge. therefore, the slave uses the first spsck edge as a start transmission signal. the ss pin can remain low between transmissions. this format may be preferable in systems having only one master and only one slave driving the miso data line. figure 6. transmission format (cpha = 1) bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb 12345678 spsck cycle # (f or reference) spsck (cpol = 0) spsck (cpol =1) mosi (from master) miso (from slave) ss (to slave) c apture strobe 10-spi_c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . spi transmission formats MC68HC708XL36 motorola spi 211 when cpha = 1 for a slave, the first edge of the spsck indicates the beginning of the transmission. this causes the spi to leave its idle state and begin driving the miso pin with the msb of its data. once the transmission begins, no new data is allowed into the shift register from the transmit data register. therefore, the spi data register of the slave must be loaded with transmit data before the first edge of spsck. any data written after the first edge is stored in the transmit data register and transferred to the shift register after the current transmission. transmission initiation latency when the spi is configured as a master (spmstr = 1), writing to the spdr starts a transmission. cpha has no effect on the delay to the start of the transmission, but it does affect the initial state of the spsck signal. when cpha = 0, the spsck signal remains inactive for the first half of the first spsck cycle. when cpha = 1, the first spsck cycle begins with an edge on the spsck line from its inactive to its active level. the spi clock rate (selected by spr1:spr0) affects the delay from the write to spdr and the start of the spi transmission. (see figure 7 on page 212.) the internal spi clock in the master is a free-running derivative of the internal mcu clock. to conserve power, it is enabled only when both the spe and spmstr bits are set. spsck edges occur halfway through the low time of the internal mcu clock. since the spi clock is free-running, it is uncertain where the write to the spdr occurs relative to the slower spsck. this uncertainty causes the variation in the initiation delay shown in figure 7 . this delay is no longer than a single spi bit time. that is, the maximum delay is two mcu bus cycles for div2, eight mcu bus cycles for div8, 32 mcu bus cycles for div32, and 128 mcu bus cycles for div128. 11-spi_c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . spi MC68HC708XL36 212 spi motorola figure 7. transmission start delay (master) write to spdr initiation delay bus mosi spsck (cpha = 1) spsck (cpha = 0) spsck cycle number msb bit 6 12 clock write to spdr earliest latest spsck = internal clock ? 2; earliest latest 2 possible start points spsck = internal clock ? 8; 8 possible start points earliest latest spsck = internal clock ? 32; 32 possible start points earliest latest spsck = internal clock ? 128; 128 possible start points write to spdr write to spdr write to spdr bus clock bit 5 3 bus clock bus clock bus clock ? ? ? ? ? ? initiation delay from write spdr to transfer begin 12-spi_c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . spi queuing transmission data MC68HC708XL36 motorola spi 213 queuing transmission data the double-buffered transmit data register allows a data byte to be queued and transmitted. for an spi configured as a master, a queued data byte is transmitted immediately after the previous transmission has completed. the spi transmitter empty flag (spte) indicates when the transmit data buffer is ready to accept new data. write to the transmit data register only when the spte bit is high. figure 8 shows the timing associated with doing back-to-back transmissions with the spi (spsck has cpha:cpol = 1:0). the transmit data buffer allows back-to-back transmissions without the slave precisely timing its writes between transmissions as in a system with a single data buffer. also, if no new data is written to the data buffer, the last value contained in the shift register is the next data word to be transmitted. figure 8. sprf/spte cpu interrupt timing bit 3 mosi spsck spte write to spdr 1 cpu writes byte 2 to spdr, queueing byte 2 cpu writes byte 1 to spdr, clearing spte bit. byte 1 transfers from transmit data 3 1 2 2 3 5 register to shift register, setting spte bit. sprf read spscr msb bit 6 bit 5 bit 4 bit 2 bit 1 lsb msb bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 lsb msb bit 6 byte 2 transfers from transmit data cpu writes byte 3 to spdr, queueing byte byte 3 transfers from transmit data 5 8 10 8 10 4 first incoming byte transfers from shift 6 cpu reads spscr with sprf bit set. 4 6 9 second incoming byte transfers from shift 9 11 and clearing spte bit. register to shift register, setting spte bit. register to receive data register, setting sprf bit. 3 and clearing spte bit. register to shift register, setting spte bit. register to receive data register, setting sprf bit. 12 cpu reads spdr, clearing sprf bit. bit 5 bit 4 byte 1 byte 2 byte 3 7 12 read spdr 7 cpu reads spdr, clearing sprf bit. 11 cpu reads spscr with sprf bit set. (cpha:cpol = 1:0) 13-spi_c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . spi MC68HC708XL36 214 spi motorola for an idle master or idle slave that has no data loaded into its transmit buffer, the spte is set again no more than two bus cycles after the transmit buffer empties into the shift register. this allows the user to queue up a 16-bit value to send. for an already active slave, the load of the shift register cannot occur until the transmission is completed. this implies that a back-to-back write to the transmit data register is not possible. the spte indicates when the next write can occur. error conditions the following flags signal spi error conditions: ? overflow (ovrf) failing to read the spi data register before the next full byte enters the shift register sets the ovrf bit. the new byte does not transfer to the receive data register, and the unread byte still can be read. ovrf is in the spi status and control register. ? mode fault error (modf) the modf bit indicates that the voltage on the slave select pin ( ss) is inconsistent with the mode of the spi. modf is in the spi status and control register. overflow error the overflow flag (ovrf) becomes set if the receive data register still has unread data from a previous transmission when the capture strobe of bit 1 of the next transmission occurs. the bit 1 capture strobe occurs in the middle of spsck cycle 7. (see figure 4 on page 209 and figure 6 on page 210.) if an overflow occurs, all data received after the overflow and before the ovrf bit is cleared does not transfer to the receive data register and does not set the spi receiver full bit (sprf). the unread data that transferred to the receive data register before the overflow occurred can still be read. therefore, an overflow error always indicates the loss of data. clear the overflow flag by reading the spi status and control register and then reading the spi data register. 14-spi_c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . spi error conditions MC68HC708XL36 motorola spi 215 ovrf generates a receiver/error cpu interrupt request if the error interrupt enable bit (errie) is also set. when the dmas bit is low, the sprf, modf, and ovrf interrupts share the same cpu interrupt vector. when the dmas bit is high, sprf generates a receiver dma service request, and modf and ovrf can generate a receiver/error cpu interrupt request. (see figure 12 on page 222.) it is not possible to enable modf or ovrf individually to generate a receiver/error cpu interrupt request. however, leaving modfen low prevents modf from being set. when the dma is enabled to service the sprf flag, it clears sprf when it reads the receive data register. the ovrf bit, however, still requires the two-step clearing mechanism of reading the flag when it is set and then reading the receive data register. in this way, the dma cannot directly clear the ovrf. however, if the cpu reads the spi status and control register with the ovrf bit set, and then the dma reads the receive data register, the ovrf bit is cleared. ovrf interrupt requests to the cpu should be enabled when using the dma to service the sprf if there is any chance that the overflow condition might occur. (see figure 9 on page 216.) even if the dma clears the sprf bit, no new data transfers from the shift register to the receive data register with the ovrf bit high. this means that no new sprf interrupt requests are generated until the cpu clears the ovrf bit. if the cpu reads the data register to clear the ovrf bit, it could clear a pending sprf service request to the dma. 15-spi_c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . spi MC68HC708XL36 216 spi motorola figure 9. overflow condition with dma service of sprf the overflow service routine may need to disable the dma and manually recover since an overflow indicates the loss of data. loss of data may prevent the dma from reaching its byte count. if an application requires the dma to bring the mcu out of wait mode, enable the ovrf bit to generate cpu interrupt requests. an overflow condition in wait mode can cause the mcu to hang in wait mode because the dma cannot reach its byte count. setting the error interrupt enable bit (errie) in the spi status and control register enables the ovrf bit to bring the mcu out of wait mode. if the cpu sprf interrupt is enabled and the ovrf interrupt is not, watch for an overflow condition. figure 10 shows how it is possible to miss an overflow. the first part of figure 10 shows how it is possible to read the spscr and spdr to clear the sprf without problems. however, as illustrated by the second transmission example, the ovrf bit can be set in between the time that spscr and spdr are read. dma reads byte 1, clearing sprf bit. byte 2 transfers from shift register to data register, setting sprf bit. 1 3 5 1 4 2 spi receive complete ovrf sprf dma read of spdr 3 4 byte 3 causes overflow. byte 3 is lost. 5 dma reads byte 2, clearing sprf bit. byte 1 byte 2 byte 3 byte 4 byte 5 byte 1 transfers from shift register to data register, 2 setting sprf bit. 6 byte 4 is lost. no new sprf dma service 6 requests and no transfers to data register until ovrf is cleared. 16-spi_c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . spi error conditions MC68HC708XL36 motorola spi 217 figure 10. missed read of overflow condition in this case, an overflow can easily be missed. since no more sprf interrupts can be generated until this ovrf is serviced, it is not obvious that bytes are being lost as more transmissions are completed. to prevent this, either enable the ovrf interrupt or do another read of the spscr following the read of the spdr. this ensures that the ovrf was not set before the sprf was cleared and that future transmissions can set the sprf bit. figure 11 illustrates this process. generally, to avoid this second spscr read, enable the ovrf to the cpu by setting the errie bit. read read ovrf sprf byte 1 byte 2 byte 3 byte 4 byte 1 sets sprf bit. cpu reads spscr with sprf bit set cpu reads byte 1 in spdr, byte 2 sets sprf bit. cpu reads spscr with sprf bit set byte 3 sets ovrf bit. byte 3 is lost. cpu reads byte 2 in spdr, clearing sprf bit , byte 4 fails to set sprf bit because 1 1 2 3 4 5 6 7 8 2 3 4 5 6 7 8 clearing sprf bit. but not ovrf bit. ovrf bit is not cleared. byte 4 is lost. and ovrf bit clear. and ovrf bit clear. spscr spdr 17-spi_c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . spi MC68HC708XL36 218 spi motorola figure 11. clearing sprf when ovrf interrupt is not enabled mode fault error setting the spmstr bit selects master mode and configures the spsck and mosi pins as outputs and the miso pin as an input. clearing spmstr selects slave mode and configures the spsck and mosi pins as inputs and the miso pin as an output. the mode fault bit, modf, becomes set any time the state of the slave select pin, ss, is inconsistent with the mode selected by spmstr. to prevent spi pin contention and damage to the mcu, a mode fault error occurs if: ? the ss pin of a slave spi goes high during a transmission. ? the ss pin of a master spi goes low at any time. for the modf flag to be set, the mode fault error enable bit (modfen) must be set. clearing the modfen bit does not clear the modf flag but does prevent modf from being set again after modf is cleared. read read ovrf sprf byte 1 byte 2 byte 3 byte 4 1 byte 1 sets sprf bit. cpu reads spscr with sprf bit set cpu reads byte 1 in spdr, cpu reads spscr again byte 2 sets sprf bit. cpu reads spscr with sprf bit set byte 3 sets ovrf bit. byte 3 is lost. cpu reads byte 2 in spdr, cpu reads spscr again cpu reads byte 2 spdr, byte 4 sets sprf bit. cpu reads spscr. cpu reads byte 4 in spdr, cpu reads spscr again 1 2 3 clearing sprf bit. 4 to check ovrf bit. 5 6 7 8 9 clearing sprf bit. to check ovrf bit. 10 clearing ovrf bit. 11 12 13 14 2 3 4 5 6 7 8 9 10 11 12 13 14 clearing sprf bit. to check ovrf bit. spi receive complete and ovrf bit clear. and ovrf bit clear. spscr spdr 18-spi_c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . spi error conditions MC68HC708XL36 motorola spi 219 modf generates a receiver/error cpu interrupt request if the error interrupt enable bit (errie) is also set. when the dmas bit is low, the sprf, modf, and ovrf interrupts share the same cpu interrupt vector. when the dmas bit is high, sprf generates a receiver dma service request instead of a cpu interrupt request, but modf and ovrf can generate a receiver/error cpu interrupt request. (see figure 12 on page 222.) it is not possible to enable modf or ovrf individually to generate a receiver/error cpu interrupt request. however, leaving modfen low prevents modf from being set. in a master spi with the mode fault enable bit (modfen) set, the mode fault flag (modf) is set if ss goes to logic 0. a mode fault in a master spi causes the following events to occur: ? if errie = 1, the spi generates an spi receiver/error cpu interrupt request. ? the spe bit is cleared. ? the spte bit is set. ? the spi state counter is cleared. ? the data direction register of the shared i/o port regains control of port drivers. note: when the modf flag is set, it does not clear the spmstr bit. the spmstr bit has no function when spe = 0. reading spmstr when modf = 1 indicates whether the spi was a master or a slave when modf became set. note: to prevent bus contention with another master spi after a mode fault error, clear all spi bits of the data direction register of the shared i/o port before enabling the spi. 19-spi_c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . spi MC68HC708XL36 220 spi motorola when configured as a slave (spmstr = 0), the modf flag is set if ss goes high during a transmission. when cpha = 0, a transmission begins when ss goes low and ends once the incoming spsck goes back to its idle level following the shift of the eighth data bit. when cpha = 1, the transmission begins when the spsck leaves its idle level and ss is already low. the transmission continues until the spsck returns to its idle level following the shift of the last data bit. (see transmission formats on page 208.) note: when cpha = 0, a modf occurs if an idle slave is selected ( ss is at logic 0) and later unselected ( ss is at logic 1) even if no spsck is sent to that slave. this happens because ss at logic 0 indicates the start of the transmission (miso driven out with the value of msb) for cpha = 0. when cpha = 1, an idle slave can be selected and then later unselected with no transmission occurring. therefore, modf does not occur since a transmission was never begun. in a slave spi (mstr = 0), the modf bit generates an spi receiver/error cpu interrupt request if the errie bit is set. the modf bit does not clear the spe bit or reset the spi in any way. software can abort the spi transmission by clearing the spe bit of the slave. note: a logic 1 voltage on the ss pin of a slave spi puts the miso pin in a high impedance state. also, the slave spi ignores all incoming spsck clocks, even if it was already in the middle of a transmission. to clear the modf flag, read the spscr with the modf bit set and then write to the spcr register. this entire clearing mechanism must occur with no modf condition existing or else the flag is not cleared. 20-spi_c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . spi interrupts MC68HC708XL36 motorola spi 221 interrupts four spi status flags can be enabled to generate cpu interrupt requests or dma service requests: the dma select bit (dmas) controls whether spte and sprf generate cpu interrupt requests or dma service requests. when dmas = 0, reading the spi status and control register with sprf set and then reading the receive data register clears sprf. when dmas = 1, any read of the receive data register clears the sprf flag. the clearing mechanism for the spte flag is always just a write to the transmit data register. the spi transmitter interrupt enable bit (sptie) enables the spte flag to generate transmitter cpu interrupt requests or transmitter dma service requests, provided that the spi is enabled (spe = 1). the spi receiver interrupt enable bit (sprie) enables the sprf bit to generate receiver cpu interrupt requests or receiver dma service requests, regardless of the state of the spe bit. (see figure 12 .) table 3. spi interrupts flag conditions for enabling interrupt request spte transmitter empty spi transmitter cpu interrupt request (dmas = 0, sptie = 1,spe = 1) spi transmitter dma service request (dmas = 1, sptie = 1, spe = 1) sprf receiver full spi receiver cpu interrupt request (dmas = 0, sprie = 1) spi receiver dma service request (dmas = 1, sprie = 1) ovrf over?ow spi receiver/error interrupt request (errie = 1) modf mode fault spi receiver/error interrupt request (errie = 1) 21-spi_c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . spi MC68HC708XL36 222 spi motorola the error interrupt enable bit (errie) enables both the modf and ovrf bits to generate a receiver/error cpu interrupt request. the mode fault enable bit (modfen) can prevent the modf flag from being set so that only the ovrf bit is enabled by the errie bit to generate receiver/error cpu interrupt requests. figure 12. spi interrupt request generation resetting the spi any system reset completely resets the spi. partial resets occur whenever the spi enable bit (spe) is low. whenever spe is low, the following occurs: ? the spte flag is set. ? any transmission currently in progress is aborted. ? the shift register is cleared. spi transmitter spte sptie sprf sprie dmas errie modf ovrf spe dma service request spi transmitter cpu interrupt request spi receiver dma service request spi receiver/error cpu interrupt request 22-spi_c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . spi low-power modes MC68HC708XL36 motorola spi 223 ? the spi state counter is cleared, making it ready for a new complete transmission. ? all the spi port logic is defaulted back to being general purpose i/o. the following items are reset only by a system reset: ? all control bits in the spcr register. ? all control bits in the spscr register (modfen, errie, spr1, and spr0). ? the status flags sprf, ovrf, and modf. by not resetting the control bits when spe is low, the user can clear spe between transmissions without having to set all control bits again when spe is set back high for the next transmission. by not resetting the sprf, ovrf, and modf flags, the user can still service these interrupts after the spi has been disabled. the user can disable the spi by writing 0 to the spe bit. the spi can also be disabled by a mode fault occuring in an spi that was configured as a master with the modfen bit set. low-power modes the wait and stop instructions put the mcu in low-power-consump- tion standby modes. wait mode the spi module remains active in wait mode. any enabled cpu interrupt request from the spi module can bring the mcu out of wait mode. if spi module functions are not required during wait mode, reduce power consumption by disabling the spi module before executing the wait instruction. the dma can service the spi without exiting wait mode. 23-spi_c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . spi MC68HC708XL36 224 spi motorola stop mode the spi module is inactive in stop mode. the stop instruction does not affect spi register states. spi operation resumes after an external interrupt. if stop mode is exited by reset, any transfer in progress is aborted, and the spi is reset. spi during break interrupts the bcfe bit in the break flag control register (bfcr) enables software to clear status bits during the break state. (see break module on page 149.) to allow software to clear status bits during a break interrupt, write a logic 1 to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break state, write a logic 0 to the bcfe bit. with bcfe at logic 0 (its default state), software can read and write i/o registers during the break state without affecting status bits. some status bits have a two-step read/write clearing procedure. if software does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is at logic 0. after the break, doing the second step clears the status bit. since the spte bit cannot be cleared during a break with the bcfe bit cleared, a write to the transmit data register in break mode does not initiate a transmission nor is this data transferred into the shift register. therefore, a write to the spdr in break mode with the bcfe bit cleared has no effect. 24-spi_c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . spi i/o signals MC68HC708XL36 motorola spi 225 i/o signals the spi module has five i/o pins and shares four of them with a parallel i/o port. ? miso master data in, slave data out ? mosi master data out, slave data in ? spsck serial clock ? ss slave select ? cgnd clock ground the spi has limited inter-integrated circuit (i 2 c) capability (requiring software support) as a master in a single-master environment. to communicate with i 2 c peripherals, mosi becomes an open-drain output when the spwom bit in the spi control register is set. in i 2 c communication, the mosi and miso pins are connected to a bidirectional pin from the i 2 c peripheral and through a pullup resistor to v dd . miso (master in/slave out) miso is one of the two spi module pins that transmits serial data. in full duplex operation, the miso pin of the master spi module is connected to the miso pin of the slave spi module. the master spi simultaneously receives data on its miso pin and transmits data from its mosi pin. slave output data on the miso pin is enabled only when the spi is configured as a slave. the spi is configured as a slave when its spmstr bit is logic 0 and its ss pin is at logic 0. to support a multiple-slave system, a logic 1 on the ss pin puts the miso pin in a high-impedance state. when enabled, the spi controls data direction of the miso pin regardless of the state of the data direction register of the shared i/o port. 25-spi_c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . spi MC68HC708XL36 226 spi motorola mosi (master out/slave in) mosi is one of the two spi module pins that transmits serial data. in full duplex operation, the mosi pin of the master spi module is connected to the mosi pin of the slave spi module. the master spi simultaneously transmits data from its mosi pin and receives data on its miso pin. when enabled, the spi controls data direction of the mosi pin regardless of the state of the data direction register of the shared i/o port. spsck (serial clock) the serial clock synchronizes data transmission between master and slave devices. in a master mcu, the spsck pin is the clock output. in a slave mcu, the spsck pin is the clock input. in full duplex operation, the master and slave mcus exchange a byte of data in eight serial clock cycles. when enabled, the spi controls data direction of the spsck pin regardless of the state of the data direction register of the shared i/o port. ss (slave select) the ss pin has various functions depending on the current state of the spi. for an spi configured as a slave, the ss is used to select a slave. for cpha = 0, the ss is used to define the start of a transmission. (see transmission formats on page 208.) since it is used to indicate the start of a transmission, the ss must be toggled high and low between each byte transmitted for the cpha = 0 format. however, it can remain low between transmissions for the cpha = 1 format. see figure 13 . figure 13. cpha/ ss timing when an spi is configured as a slave, the ss pin is always configured as an input. it cannot be used as a general-purpose i/o regardless of the byte 1 byte 3 miso/mosi byte 2 master ss slave ss (cpha = 0) slave ss (cpha = 1) 26-spi_c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . spi i/o signals MC68HC708XL36 motorola spi 227 state of the modfen control bit. however, the modfen bit can still prevent the state of the ss from creating a modf error. (see spi status and control register on page 230.) note: a logic 1 voltage on the ss pin of a slave spi puts the miso pin in a high-impedance state. the slave spi ignores all incoming spsck clocks, even if it was already in the middle of a transmission. when an spi is configured as a master, the ss input can be used in conjunction with the modf flag to prevent multiple masters from driving mosi and spsck. (see mode fault error on page 218.) for the state of the ss pin to set the modf flag, the modfen bit in the spsck register must be set. if the modfen bit is low for an spi master, the ss pin can be used as a general-purpose i/o under the control of the data direction register of the shared i/o port. with modfen high, it is an input-only pin to the spi regardless of the state of the data direction register of the shared i/o port. the cpu can always read the state of the ss pin by configuring the appropriate pin as an input and reading the port data register. (see table 4 .) 1. x = dont care cgnd (clock ground) cgnd is the ground return for the serial clock pin, spsck, and the ground for the port output buffers. to reduce the ground return path loop and minimize radio frequency (rf) emissions, connect the ground pin of the slave to the cgnd pin of the master. table 4. spi con?guration spe spmstr modfen spi configuration state of ss logic 0x (1) x not enabled general-purpose i/o; ss ignored by spi 1 0 x slave input-only to spi 1 1 0 master without modf general-purpose i/o; ss ignored by spi 1 1 1 master with modf input-only to spi 27-spi_c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . spi MC68HC708XL36 228 spi motorola i/o registers three registers control and monitor spi operation: ? spi control register (spcr) ? spi status and control register (spscr) ? spi data register (spdr) spi control register the spi control register does the following: ? enables spi module interrupt requests ? selects cpu interrupt requests or dma service requests ? configures the spi module as master or slave ? selects serial clock polarity and phase ? configures the spsck, mosi, and miso pins as open-drain outputs ? enables the spi module sprie spi receiver interrupt enable bit this read/write bit enables cpu interrupt requests or dma service requests generated by the sprf bit. the sprf bit is set when a byte transfers from the shift register to the receive data register. reset clears the sprie bit. 1 = sprf cpu interrupt requests or sprf dma service requests enabled 0 = sprf cpu interrupt requests or sprf dma service requests disabled address: $0010 bit 7 654321 bit 0 read: sprie dmas spmstr cpol cpha spwom spe sptie write: reset: 00101000 figure 14. spi control register (spcr) 28-spi_c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . spi i/o registers MC68HC708XL36 motorola spi 229 dmas dma select bit this read/write bit selects dma service requests when: ? the spi receiver full bit, sprf, becomes set and the spi receiver interrupt enable bit, spie, is also set ? the spi transmitter empty bit, spte, becomes set and the spi transmitter interrupt enable bit, sptie, is also set setting the dmas bit disables sprf cpu interrupt requests and spte cpu interrupt requests. reset clears the dmas bit. 1 = sprf dma and spte dma service requests selected sprf cpu and spte cpu interrupt requests disabled 0 = sprf dma and spte dma service requests disabled sprf cpu and spte cpu interrupt requests selected spmstr spi master bit this read/write bit selects master mode operation or slave mode operation. reset sets the spmstr bit. 1 = master mode 0 = slave mode cpol clock polarity bit this read/write bit determines the logic state of the spsck pin between transmissions. (see figure 4 on page 209 and figure 6 on page 210.) to transmit data between spi modules, the spi modules must have identical cpol values. reset clears the cpol bit. cpha clock phase bit this read/write bit controls the timing relationship between the serial clock and spi data. (see figure 4 on page 209 and figure 6 on page 210.) to transmit data between spi modules, the spi modules must have identical cpha values. when cpha = 0, the ss pin of the slave spi module must be set to logic 1 between bytes. (see figure 13 on page 226.) reset sets the cpha bit. 29-spi_c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . spi MC68HC708XL36 230 spi motorola spwom spi wired-or mode bit this read/write bit disables the pullup devices on pins spsck, mosi, and miso so that those pins become open-drain outputs. 1 = wired-or spsck, mosi, and miso pins 0 = normal push-pull spsck, mosi, and miso pins spe spi enable this read/write bit enables the spi module. clearing spe causes a partial reset of the spi. (see resetting the spi on page 222.) reset clears the spe bit. 1 = spi module enabled 0 = spi module disabled sptie spi transmit interrupt enable this read/write bit enables cpu interrupt requests or dma service requests generated by the spte bit. spte is set when a byte transfers from the transmit data register to the shift register. reset clears the sptie bit. 1 = spte cpu interrupt requests or spte dma service requests enabled 0 = spte cpu interrupt requests or spte dma service requests disabled spi status and control register the spi status and control register contains flags to signal the following conditions: ? receive data register full ? failure to clear sprf bit before next byte is received (overflow error) ? inconsistent logic level on ss pin (mode fault error) ? transmit data register empty the spi status and control register also contains bits that perform the following functions: ? enable error interrupts ? enable mode fault error detection ? select master spi baud rate 30-spi_c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . spi i/o registers MC68HC708XL36 motorola spi 231 sprf spi receiver full bit this clearable, read-only flag is set each time a byte transfers from the shift register to the receive data register. sprf generates a cpu interrupt request or a dma service request if the sprie bit in the spi control register is set also. the dma select bit (dmas) in the spi control register determines whether sprf generates an sprf cpu interrupt request or an sprf dma service request. during an sprf cpu interrupt (dmas = 0), the cpu clears sprf by reading the spi status and control register with sprf set and then reading the spi data register. during an sprf dma transmission (dmas = 1), any read of the spi data register clears the sprf bit. reset clears the sprf bit. 1 = receive data register full 0 = receive data register not full note: when the dma is configured to service the spi (dmas = 1), a read by the cpu of the receive data register can inadvertently clear the sprf bit and cause the dma to miss a service request. errie error interrupt enable bit this read/write bit enables the modf and ovrf bits to generate cpu interrupt requests. reset clears the errie bit. 1 = modf and ovrf can generate cpu interrupt requests 0 = modf and ovrf cannot generate cpu interrupt requests address: $0011 bit 7 654321 bit 0 read: sprf errie ovrf modf spte modfen spr1 spr0 write: reset: 00001000 = unimplemented figure 15. spi status and control register (spscr) 31-spi_c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . spi MC68HC708XL36 232 spi motorola ovrf overflow bit this clearable, read-only flag is set if software does not read the byte in the receive data register before the next full byte enters the shift register. in an overflow condition, the byte already in the receive data register is unaffected, and the byte that shifted in last is lost. clear the ovrf bit by reading the spi status and control register with ovrf set and then reading the receive data register. reset clears the ovrf bit. 1 = overflow 0 = no overflow modf mode fault bit this clearable, read-only flag is set in a slave spi if the ss pin goes high during a transmission with the modfen bit set. in a master spi, the modf flag is set if the ss pin goes low at any time with the modfen bit set. clear the modf bit by reading the spi status and control register (spscr) with modf set and then writing to the spi control register (spcr). reset clears the modf bit. 1 = ss pin at inappropriate logic level 0 = ss pin at appropriate logic level spte spi transmitter empty bit this clearable, read-only flag is set each time the transmit data register transfers a byte into the shift register. spte generates an spte cpu interrupt request or an spte dma service request if the sptie bit in the spi control register is set also. note: do not write to the spi data register unless the spte bit is high. the dma select bit (dmas) in the spi control register determines whether spte generates an spte cpu interrupt request or an spte dma service request. during an spte cpu interrupt (dmas = 0), the cpu clears the spte bit by writing to the transmit data register. during an spte dma transmission (dmas = 1), the dma automatically clears spte when it writes to the transmit data register. note: when the dma is configured to service the spi (dmas = 1), a write by the cpu to the transmit data register can inadvertently clear the spte bit and cause the dma to miss a service request. 32-spi_c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . spi i/o registers MC68HC708XL36 motorola spi 233 reset sets the spte bit. 1 = transmit data register empty 0 = transmit data register not empty modfen mode fault enable bit this read/write bit, when set to 1, allows the modf flag to be set. if the modf flag is set, clearing the modfen does not clear the modf flag. if the spi is enabled as a master and the modfen bit is low, then the ss pin is available for general-purpose i/o. if the modfen bit is set, then this pin is not available for general-purpose i/o. when the spi is enabled as a slave, the ss pin is not available as a general purpose i/o regardless of the value of modfen. (see ss (slave select) on page 226.) if the modfen bit is low, the level of the ss pin does not affect the operation of an enabled spi configured as a master. for an enabled spi configured as a slave, having modfen low only prevents the modf flag from being set. it does not affect any other part of spi operation. (see mode fault error on page 218.) spr1 and spr0 spi baud rate select bits in master mode, these read/write bits select one of four baud rates as shown in table 5 . spr1 and spr0 have no effect in slave mode. reset clears spr1 and spr0. use the following formula to calculate the spi baud rate: where: cgmout = base clock output of the clock generator module (cgm) bd = baud rate divisor table 5. spi master baud rate selection spr1:spr0 baud rate divisor (bd) 00 2 01 8 10 32 11 128 baud rate bus clock bd ---------------------------------- = 33-spi_c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . spi MC68HC708XL36 234 spi motorola spi data register the spi data register consists of the read-only receive data register and the write-only transmit data register. writing to the spi data register writes data into the transmit data register. reading the spi data register reads data from the receive data register. the transmit data and receive data registers are separate registers that can contain different values. (see figure 1 on page 204.) r7:r0/t7:t0 receive/transmit data bits note: do not use read-modify-write instructions on the spi data register since the register read is not the same as the register written. address: $0012 bit 7 654321 bit 0 read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: indeterminate after reset figure 16. spi data register (spdr) 34-spi_c f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC708XL36 motorola sci 235 serial communications interface module sci contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .236 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .237 pin name conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .238 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241 transmitter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241 character transmission . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .241 break characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245 idle characters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .245 inversion of transmitted output . . . . . . . . . . . . . . . . . . . . . . . .246 transmitter interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .246 receiver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .247 character length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249 character reception . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249 data sampling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .249 framing errors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252 baud rate tolerance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .252 receiver wakeup . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .256 receiver interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .257 error interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .258 error flags during dma service requests . . . . . . . . . . . . . . .259 low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261 stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .261 sci during break module interrupts . . . . . . . . . . . . . . . . . . . . . . . . .262 1-sci_d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sci MC68HC708XL36 236 sci motorola i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263 txd (transmit data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263 rxd (receive data) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .263 sci control register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .264 sci control register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .267 sci control register 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .270 sci status register 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .273 sci status register 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .277 sci data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .278 sci baud rate register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .279 introduction the sci allows asynchronous communications with peripheral devices and other mcus. 2-sci_d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sci features MC68HC708XL36 motorola sci 237 features ? full duplex operation ? standard mark/space non-return-to-zero (nrz) format ? 32 programmable baud rates ? programmable 8-bit or 9-bit character length ? separately enabled transmitter and receiver ? separate receiver and transmitter cpu interrupt requests ? separate receiver and transmitter dma service requests ? programmable transmitter output polarity ? two receiver wakeup methods: C idle line wakeup C address mark wakeup ? interrupt-driven operation with eight interrupt flags: C transmitter empty C transmission complete C receiver full C idle receiver input C receiver overrun C noise error C framing error C parity error ? receiver framing error detection ? hardware parity checking ? 1/16 bit-time noise detection 3-sci_d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sci MC68HC708XL36 238 sci motorola pin name conventions the generic names of the sci i/o pins are: ? rxd (receive data) ? txd (transmit data) sci i/o lines are implemented by sharing parallel i/o port pins. the full name of an sci input or output reflects the name of the shared port pin. table 1 shows the full names and the generic names of the sci i/o pins.the generic pin names appear in the text of this section. functional description figure 1 shows the structure of the sci module. the sci allows full-duplex, asynchronous, nrz serial communication between the mcu and remote devices, including other mcus. the transmitter and receiver of the sci operate independently, although they use the same baud rate generator. during normal operation, the cpu monitors the status of the sci, writes the data to be transmitted, and processes received data. during dma transfers, the dma fetches data from memory for the sci to transmit and/or the dma stores received data in memory. table 1. pin name conventions generic pin names rxd txd full pin names pe1/rxd pe2/txd 4-sci_d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sci functional description MC68HC708XL36 motorola sci 239 figure 1. sci module block diagram scte tc scrf idle or nf fe pe sctie tcie scrie ilie te re rwu sbk r8 t8 dmate orie feie peie bkf rpf sci data receive shift register sci data register transmit shift register neie m wake ilty flag control transmit control receive control data selection control wakeup pty pen register dma interrupt control transmitter interrupt control receiver interrupt control error interrupt control control dmare ensci loops ensci internal bus txinv loops ? 4 ? 16 pre- scaler baud rate generator cgmxclk rxd txd 5-sci_d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sci MC68HC708XL36 240 sci motorola register name bit 7 654321 bit 0 sci control register 1 (scc1) read: loops ensci txinv m wake ilty pen pty write: reset: 00000000 sci control register 2 (scc2) read: sctie tcie scrie ilie te re rwu sbk write: reset: 00000000 sci control register 3 (scc3) read: r8 t8 dmare dmate orie neie feie peie write: reset: u u 000000 sci status register 1 (scs1) read: scte tc scrf idle or nf fe pe write: reset: 11000000 sci status register 2 (scs2) read: bkf rpf write: reset: 00000000 sci data register (scdr) read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset sci baud rate register (scbr) read: scp1 scp0 r scr2 scr1 scr0 write: reset: 00000000 = unimplemented u = unaffected r = reserved figure 2. sci i/o register summary table 2. sci i/o register address summary register scc1 scc2 scc3 scs1 scs2 scdr scbr address $0013 $0014 $0015 $0016 $0017 $0018 $0019 6-sci_d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sci functional description MC68HC708XL36 motorola sci 241 data format the sci uses the standard non-return-to-zero mark/space data format illustrated in figure 3 . figure 3. sci data formats transmitter figure 4 shows the structure of the sci transmitter. character length the transmitter can accommodate either 8-bit or 9-bit data. the state of the m bit in sci control register 1 (scc1) determines character length. when transmitting 9-bit data, bit t8 in sci control register 3 (scc3) is the ninth bit (bit 8). character transmission during an sci transmission, the transmit shift register shifts a character out to the txd pin. the sci data register (scdr) is the write-only buffer between the internal data bus and the transmit shift register. to initiate an sci transmission: 1. enable the sci by writing a logic 1 to the enable sci bit (ensci) in sci control register 1 (scc1). 2. enable the transmitter by writing a logic 1 to the transmitter enable bit (te) in sci control register 2 (scc2). 3. clear the sci transmitter empty bit by first reading sci status register 1 (scs1) and then writing to the scdr. in a dma transfer, the dma automatically clears the scte bit by writing to the scdr. 4. repeat step 3 for each subsequent transmission. bit 5 start bit bit 0 bit 1 next stop bit start bit 8-bit data format (bit m in scc1 clear) start bit bit 0 next stop bit start bit 9-bit data format (bit m in scc1 set) bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 2 bit 3 bit 4 bit 6 bit 7 parity or data bit parity or data bit 7-sci_d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sci MC68HC708XL36 242 sci motorola at the start of a transmission, transmitter control logic automatically loads the transmit shift register with a preamble of logic 1s. after the preamble shifts out, control logic transfers the scdr data into the transmit shift register. a logic 0 start bit automatically goes into the least significant bit position of the transmit shift register. a logic 1 stop bit goes into the most significant bit position. the sci transmitter empty bit, scte, in scs1 becomes set when the scdr transfers a byte to the transmit shift register. the scte bit indicates that the scdr can accept new data from the internal data bus. if the sci transmit interrupt enable bit, sctie, in scc2 is also set, the scte bit generates a transmitter cpu interrupt request or a transmitter dma service request. the scte bit generates a transmitter dma service request if the dma transfer enable bit, dmate, in sci control register 3 (scc3) is set. setting the dmate bit enables the scte bit to generate transmitter dma service requests and disables transmitter cpu interrupt requests. when the transmit shift register is not transmitting a character, the txd pin goes to the idle condition, logic 1. if at any time software clears the ensci bit in sci control register 1 (scc1), the transmitter and receiver relinquish control of the port e pins. 8-sci_d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sci functional description MC68HC708XL36 motorola sci 243 figure 4. sci transmitter dmate scte pen pty h876543210l 11-bit transmit stop start t8 dmate scte sctie tcie sbk tc cgmxclk parity generation msb sci data register load from scdr shift enable preamble (all ones) break (all zeros) transmitter control logic shift register dmate tc sctie tcie scte transmitter cpu interrupt request transmitter dma service request m ensci loops te txinv internal bus ? 4 pre- scaler scp1 scp0 scr2 scr1 scr0 baud divider ? 16 sctie txd 9-sci_d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sci MC68HC708XL36 244 sci motorola register name bit 7 654321 bit 0 sci control register 1 (scc1) read: loops ensci txinv m wake ilty pen pty write: reset: 00000000 sci control register 2 (scc2) read: sctie tcie scrie ilie te re rwu sbk write: reset: 00000000 sci control register 3 (scc3) read: r8 t8 dmare dmate orie neie feie peie write: reset: u u 000000 sci status register 1 (scs1) read: scte tc scrf idle or nf fe pe write: reset: 11000000 sci data register (scdr) read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset sci baud rate register (scbr) read: scp1 scp0 r scr2 scr1 scr0 write: reset: 00000000 = unimplemented u = unaffected r = reserved figure 5. sci transmitter i/o register summary table 3. sci transmitter i/o address summary register scc1 scc2 scc3 scs1 scdr scbr address $0013 $0014 $0015 $0016 $0018 $0019 10-sci_d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sci functional description MC68HC708XL36 motorola sci 245 break characters writing a logic 1 to the send break bit, sbk, in scc2 loads the transmit shift register with a break character. a break character contains all logic zeros and has no start, stop, or parity bit. break character length depends on the m bit in scc1. as long as sbk is at logic 1, transmitter logic continuously loads break characters into the transmit shift register. after software clears the sbk bit, the shift register finishes transmitting the last break character and then transmits at least one logic 1. the automatic logic 1 at the end of a break character guarantees the recognition of the start bit of the next character. the sci recognizes a break character when a start bit is followed by eight or nine logic 0 data bits and a logic 0 where the stop bit should be. receiving a break character has the following effects on sci registers: ? sets the framing error bit (fe) in scs1 ? sets the sci receiver full bit (scrf) in scs1 ? clears the sci data register (scdr) ? clears the r8 bit in scc3 ? sets the break flag bit (bkf) in scs2 ? may set the overrun (or), noise flag (nf), parity error (pe), or reception in progress flag (rpf) bits idle characters an idle character contains all logic 1s and has no start, stop, or parity bit. idle character length depends on the m bit in scc1. the preamble is a synchronizing idle character that begins every transmission. if the te bit is cleared during a transmission, the txd pin becomes idle after completion of the transmission in progress. clearing and then setting the te bit during a transmission queues an idle character to be sent after the character currently being transmitted. 11-sci_d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sci MC68HC708XL36 246 sci motorola note: when queueing an idle character, return the te bit to logic 1 before the stop bit of the current character shifts out to the txd pin. setting te after the stop bit appears on txd causes data previously written to the scdr to be lost. a good time to toggle the te bit for a queued idle character is when the scte bit becomes set and just before writing the next byte to the scdr. inversion of transmitted output the transmit inversion bit (txinv) in sci control register 1 (scc1) reverses the polarity of transmitted data. all transmitted values, including idle, break, start, and stop bits, are inverted when txinv is at logic 1. (see sci control register 1 on page 264.) transmitter interrupts the following conditions can generate cpu interrupt requests from the sci transmitter: ? sci transmitter empty (scte) the scte bit in scs1 indicates that the scdr has transferred a character to the transmit shift register. scte can generate a transmitter cpu interrupt request or a transmitter dma service request. setting the sci transmit interrupt enable bit, sctie, in scc2 enables the scte bit to generate transmitter cpu interrupt requests. setting both the sctie bit and the dma transfer enable bit, dmate, in scc3 enables the scte bit to generate transmitter dma service requests. ? transmission complete (tc) the tc bit in scs1 indicates that the transmit shift register and the scdr are empty and that no break or idle character has been generated. the transmission complete interrupt enable bit, tcie, in scc2 enables the tc bit to generate transmitter cpu interrupt requests. 12-sci_d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sci functional description MC68HC708XL36 motorola sci 247 receiver figure 6 shows the structure of the sci receiver. figure 6. sci receiver block diagram all ones all zeros m wake ilty pen pty bkf rpf h876543210l 11-bit receive shift register stop start data recovery dmare scrf or orie nf neie fe feie pe peie dmare scrie scrf ilie idle wakeup logic parity checking msb error cpu interrupt request dma service request cpu interrupt request sci data register r8 dmare orie neie feie peie scrie ilie rwu scrf idle or nf fe pe internal bus pre- scaler baud divider ? 4 ? 16 scp1 scp0 scr2 scr1 scr0 cgmxclk scrie dmare rxd 13-sci_d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sci MC68HC708XL36 248 sci motorola register name bit 7 654321 bit 0 sci control register 1 (scc1) read: loops ensci txinv m wake ilty pen pty write: reset: 00000000 sci control register 2 (scc2) read: sctie tcie scrie ilie te re rwu sbk write: reset: 00000000 sci control register 3 (scc3) read: r8 t8 dmare dmate orie neie feie peie write: reset: u u 000000 sci status register 1 (scs1) read: scte tc scrf idle or nf fe pe write: reset: 11000000 sci status register 2 (scs2) read: bkf rpf write: reset: 00000000 sci data register (scdr) read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset sci baud rate register (scbr) read: scp1 scp0 r scr2 scr1 scr0 write: reset: 00000000 = unimplemented u = unaffected r = reserved figure 7. sci i/o register summary table 4. sci receiver i/o address summary register scc1 scc2 scc3 scs1 scs2 scdr scbr address $0013 $0014 $0015 $0016 $0017 $0018 $0019 14-sci_d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sci functional description MC68HC708XL36 motorola sci 249 character length the receiver can accommodate either 8-bit or 9-bit data. the state of the m bit in sci control register 1 (scc1) determines character length. when receiving 9-bit data, bit r8 in sci control register 2 (scc2) is the ninth bit (bit 8). when receiving 8-bit data, bit r8 is a copy of the eighth bit (bit 7). character reception during an sci reception, the receive shift register shifts characters in from the rxd pin. the sci data register (scdr) is the read-only buffer between the internal data bus and the receive shift register. after a complete character shifts into the receive shift register, the data portion of the character transfers to the scdr. the sci receiver full bit, scrf, in sci status register 1 (scs1) becomes set, indicating that the received byte can be read. if the sci receive interrupt enable bit, scrie, in scc2 is also set, the scrf bit generates a receiver cpu interrupt request or a receiver dma service request. the scrf bit generates a receiver dma service request if the dma receive enable bit, dmare, in sci control register 3 (scc3) is set. setting the dmare bit enables the scrf bit to generate receiver dma service requests and disables receiver cpu interrupt requests. data sampling the receiver samples the rxd pin at the rt clock rate. the rt clock is an internal signal with a frequency 16 times the baud rate. to adjust for baud rate mismatch, the rt clock is resynchronized at the following times (see figure 8 ): ? after every start bit ? after the receiver detects a data bit change from logic 1 to logic 0 (after the majority of data bit samples at rt8, rt9, and rt10 returns a valid logic 1 and the majority of the next rt8, rt9, and rt10 samples returns a valid logic 0) to locate the start bit, data recovery logic does an asynchronous search for a logic 0 preceded by three logic 1s. when the falling edge of a possible start bit occurs, the rt clock begins to count to 16. 15-sci_d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sci MC68HC708XL36 250 sci motorola figure 8. receiver data sampling to verify the start bit and to detect noise, data recovery logic takes samples at rt3, rt5, and rt7. table 5 summarizes the results of the start bit verification samples. if start bit verification is not successful, the rt clock is reset and a new search for a start bit begins. table 5. start bit veri?cation rt3, rt5, and rt7 samples start bit verification noise flag 000 yes 0 001 yes 1 010 yes 1 011 no 0 100 yes 1 101 no 0 110 no 0 111 no 0 rt clock reset rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt1 rt2 rt3 rt4 rt5 rt8 rt7 rt6 rt11 rt10 rt9 rt15 rt14 rt13 rt12 rt16 rt1 rt2 rt3 rt4 start bit qualification start bit verification data sampling samples rt clock rt clock state start bit lsb rxd 16-sci_d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sci functional description MC68HC708XL36 motorola sci 251 to determine the value of a data bit and to detect noise, recovery logic takes samples at rt8, rt9, and rt10. table 6 summarizes the results of the data bit samples. note: the rt8, rt9, and rt10 samples do not affect start bit verification. if any or all of the rt8, rt9, and rt10 start bit samples are logic 1s following a successful start bit verification, the noise flag (nf) is set and the receiver assumes that the bit is a start bit. table 6. data bit recovery rt8, rt9, and rt10 samples data bit determination noise flag 000 0 0 001 0 1 010 0 1 011 1 1 100 0 1 101 1 1 110 1 1 111 1 0 17-sci_d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sci MC68HC708XL36 252 sci motorola to verify a stop bit and to detect noise, recovery logic takes samples at rt8, rt9, and rt10. table 7 summarizes the results of the stop bit samples. framing errors if the data recovery logic does not detect a logic 1 where the stop bit should be in an incoming character, it sets the framing error bit, fe, in scs1. a break character also sets the fe bit because a break character has no stop bit. the fe bit is set at the same time that the scrf bit is set. baud rate tolerance a transmitting device may be operating at a baud rate below or above the receiver baud rate. accumulated bit time misalignment can cause one of the three stop bit data samples to fall outside the actual stop bit. then a noise error occurs. if more than one of the samples is outside the stop bit, a framing error occurs. in most applications, the baud rate tolerance is much more than the degree of misalignment that is likely to occur. as the receiver samples an incoming character, it resynchronizes the rt clock on any valid falling edge within the character. resynchronization within characters corrects misalignments between transmitter bit times and receiver bit times. table 7. stop bit recovery rt8, rt9, and rt10 samples framing error flag noise flag 000 1 0 001 1 1 010 1 1 011 0 1 100 1 1 101 0 1 110 0 1 111 0 0 18-sci_d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sci functional description MC68HC708XL36 motorola sci 253 slow data tolerance figure 9 shows how much a slow received character can be misaligned without causing a noise error or a framing error. the slow stop bit begins at rt8 instead of rt1 but arrives in time for the stop bit data samples at rt8, rt9, and rt10. figure 9. slow data for an 8-bit character, data sampling of the stop bit takes the receiver 9 bit times 16 rt cycles + 10 rt cycles = 154 rt cycles. with the misaligned character shown in figure 9 , the receiver counts 154 rt cycles at the point when the count of the transmitting device is 9 bit times 16 rt cycle s+3rt cycles = 147 rt cycles. the maximum percent difference between the receiver count and the transmitter count of a slow 8-bit character with no errors is for a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times 16 rt cycles + 10 rt cycles = 170 rt cycles. with the misaligned character shown in figure 9 , the receiver counts 170 rt cycles at the point when the count of the transmitting device is 10 bit times 16 rt cycle s+3rt cycles = 163 rt cycles. msb stop rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt11 rt12 rt13 rt14 rt15 rt16 data samples receiver rt clock 154 147 C 154 ------------------------- - 100 4.54% = 19-sci_d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sci MC68HC708XL36 254 sci motorola the maximum percent difference between the receiver count and the transmitter count of a slow 9-bit character with no errors is fast data tolerance figure 10 shows how much a fast received character can be misaligned without causing a noise error or a framing error. the fast stop bit ends at rt10 instead of rt16 but is still there for the stop bit data samples at rt8, rt9, and rt10. figure 10. fast data for an 8-bit character, data sampling of the stop bit takes the receiver 9 bit times 16 rt cycles + 10 rt cycles = 154 rt cycles. with the misaligned character shown in figure 10 , the receiver counts 154 rt cycles at the point when the count of the transmitting device is 10 bit times 16 rt cycles = 160 rt cycles. the maximum percent difference between the receiver count and the transmitter count of a fast 8-bit character with no errors is for a 9-bit character, data sampling of the stop bit takes the receiver 10 bit times 16 rt cycles + 10 rt cycles = 170 rt cycles. 170 163 C 170 ------------------------- - 100 4.12% = idle or next character stop rt1 rt2 rt3 rt4 rt5 rt6 rt7 rt8 rt9 rt10 rt11 rt12 rt13 rt14 rt15 rt16 data samples receiver rt clock 20-sci_d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sci functional description MC68HC708XL36 motorola sci 255 with the misaligned character shown in figure 10 , the receiver counts 170 rt cycles at the point when the count of the transmitting device is 11 bit times 16 rt cycles = 176 rt cycles. the maximum percent difference between the receiver count and the transmitter count of a fast 9-bit character with no errors is 154 160 C 154 ------------------------- - 100 3.90% B = 170 176 C 170 ------------------------- - 100 3.53% = 21-sci_d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sci MC68HC708XL36 256 sci motorola receiver wakeup so that the mcu can ignore transmissions intended only for other receivers in multiple-receiver systems, the receiver can be put into a standby state. setting the receiver wakeup bit, rwu, in scc2 puts the receiver into a standby state during which receiver interrupts are disabled. depending on the state of the wake bit in scc1, either of two conditions on the rxd pin can bring the receiver out of the standby state: ? address mark an address mark is a logic 1 in the most significant bit position of a received character. when the wake bit is set, an address mark wakes the receiver from the standby state by clearing the rwu bit. the address mark also sets the sci receiver full bit, scrf. software can then compare the character containing the address mark to the user-defined address of the receiver. if they are the same, the receiver remains awake and processes the characters that follow. if they are not the same, software can set the rwu bit and put the receiver back into the standby state. ? idle input line condition when the wake bit is clear, an idle character on the rxd pin wakes the receiver from the standby state by clearing the rwu bit. the idle character that wakes the receiver does not set the receiver idle bit, idle, or the sci receiver full bit, scrf. the idle line type bit, ilty, determines whether the receiver begins counting logic ones as idle character bits after the start bit or after the stop bit. note: with the wake bit clear, setting the rwu bit after the rxd pin has been idle may cause the receiver to wake up immediately. 22-sci_d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sci functional description MC68HC708XL36 motorola sci 257 receiver interrupts the following sources can generate cpu interrupt requests from the sci receiver: ? sci receiver full (scrf) the scrf bit in scs1 indicates that the receive shift register has transferred a character to the scdr. scrf can generate a receiver cpu interrupt request or a receiver dma service request. setting the sci receive interrupt enable bit, scrie, in scc2 enables the scrf bit to generate receiver cpu interrupts. setting both the scrie bit and the dma receive enable bit, dmare, in scc3 enables receiver dma service requests and disables receiver cpu interrupt requests. ? idle input (idle) the idle bit in scs1 indicates that 10 or 11 consecutive logic 1s shifted in from the rxd pin. the idle line interrupt enable bit, ilie, in scc2 enables the idle bit to generate cpu interrupt requests. note: when receiver dma service requests are enabled (dmare = 1), then receiver cpu interrupt requests are disabled. 23-sci_d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sci MC68HC708XL36 258 sci motorola error interrupts the following receiver error flags in scs1 can generate cpu interrupt requests: ? receiver overrun (or) the or bit indicates that the receive shift register shifted in a new character before the previous character was read from the scdr. the previous character remains in the scdr, and the new character is lost. the overrun interrupt enable bit, orie, in scc3 enables or to generate sci error cpu interrupt requests. ? noise flag (nf) the nf bit is set when the sci detects noise on incoming data or break characters, including start, data, and stop bits. the noise error interrupt enable bit, neie, in scc3 enables nf to generate sci error cpu interrupt requests. ? framing error (fe) the fe bit in scs1 is set when a logic 0 occurs where the receiver expects a stop bit. the framing error interrupt enable bit, feie, in scc3 enables fe to generate sci error cpu interrupt requests. ? parity error (pe) the pe bit in scs1 is set when the sci detects a parity error in incoming data. the parity error interrupt enable bit, peie, in scc3 enables pe to generate sci error cpu interrupt requests. 24-sci_d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sci functional description MC68HC708XL36 motorola sci 259 error flags during dma service requests when the dma is servicing the sci receiver, it clears the scrf bit when it reads the sci data register. the dma does not clear the other status bits (bkf or rpf), nor does it clear error flags (or, nf, fe, and pe). to clear error flags while the dma is servicing the receiver, enable sci error cpu interrupts and clear the bits in an interrupt routine. the application may require retransmission in case of error. if the application requires the receptions to continue, note the following latency considerations: 1. if interrupt latency is short enough for an error bit to be serviced before the next scrf, then it can be determined which byte caused the error. if interrupt latency is long enough for a new scrf to occur before servicing an error bit, then: a. it cannot be determined whether the error bit being serviced is due to the byte in the sci data register or to a previous byte. multiple errors can accumulate that correspond to different bytes. in a message-based system, you may have to repeat the entire message. b. when the dma is enabled to service the sci receiver, merely reading the sci data register clears the scrf bit. the second step in clearing an error bit, reading the sci data register, could inadvertently clear a new, unserviced scrf that occurred during the error-servicing routine. then the dma would ignore the byte that set the new scrf, and the new byte would be lost. to prevent clearing of an unserviced scrf bit, clear the scrie bit at the beginning of the error-servicing interrupt routine and set it at the end. clearing scrie disables dma service so that both a read of scs1 and a read of scdr are required to clear the scrf bit. setting scrie enables dma service so that the dma can recognize a service request that occurred during the error-servicing interrupt routine. c. in the cpu interrupt routine to service error bits, do not use brset or brclr instructions. brset and brclr read the scs1 register, which is the first step in clearing the register. 25-sci_d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sci MC68HC708XL36 260 sci motorola then the dma could read the sci data register, the second step in clearing it, thereby clearing all error bits. the next read of the data register would miss any error bits that were set. 2. dma latency should be short enough so that an scrf is serviced before the next scrf occurs. if dma latency is long enough for a new scrf to occur before servicing an error bit, then: a. overruns occur. set the orie bit to enable sci error cpu interrupt requests and service the overrun in an interrupt routine. in a message-based system, disable the dma in the interrupt routine and manually recover. otherwise, the byte that was lost in the overrun could prevent the dma from reaching its byte count. if the dma reaches it byte count in the following message, two messages may be corrupted. b. if the cpu does not service an overrun interrupt request, the dma can eventually clear the scrf bit by reading the sci data register. the or bit remains set. each time a new byte sets the scrf bit, new data transfers from the shift register to the sci data register (provided that another overrun does not occur), even though the or bit is set. the dma removed the overrun condition by reading the data register, but the or bit has not been cleared. 26-sci_d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sci low-power modes MC68HC708XL36 motorola sci 261 low-power modes the wait and stop instructions put the mcu in low-power-consump- tion standby modes. wait mode the sci module remains active in wait mode. any enabled cpu interrupt request from the sci module can bring the mcu out of wait mode. if sci module functions are not required during wait mode, reduce power consumption by disabling the module before executing the wait instruction. the dma can service the sci without exiting wait mode. stop mode the sci module is inactive in stop mode. the stop instruction does not affect sci register states. sci module operation resumes after the mcu exits stop mode. because the internal clock is inactive during stop mode, entering stop mode during an sci transmission or reception results in invalid data. 27-sci_d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sci MC68HC708XL36 262 sci motorola sci during break module interrupts the bcfe bit in the break flag control register (bfcr) enables software to clear status bits during the break state. (see break module on page 149.) to allow software to clear status bits during a break interrupt, write a logic 1 to the bcfe bit. if a status bit is cleared during the break state, it remains cleared when the mcu exits the break state. to protect status bits during the break state, write a logic 0 to the bcfe bit. with bcfe at logic 0 (its default state), software can read and write i/o registers during the break state without affecting status bits. some status bits have a two-step read/write clearing procedure. if software does the first step on such a bit before the break, the bit cannot change during the break state as long as bcfe is at logic 0. after the break, doing the second step clears the status bit. 28-sci_d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sci i/o signals MC68HC708XL36 motorola sci 263 i/o signals port e shares two of its pins with the sci module. the two sci i/o pins are: ? txd transmit data ? rxd receive data txd (transmit data) the txd pin is the serial data output from the sci transmitter. the sci shares the txd pin with port e. when the sci is enabled, the txd pin is an output regardless of the state of the ddre2 bit in data direction register e (ddre). rxd (rec eive data) the rxd pin is the serial data input to the sci receiver. the sci shares the rxd pin with port e. when the sci is enabled, the rxd pin is an input regardless of the state of the ddre1 bit in data direction register e (ddre). i/o registers the following i/o registers control and monitor sci operation: ? sci control register 1 (scc1) ? sci control register 2 (scc2) ? sci control register 3 (scc3) ? sci status register 1 (scs1) ? sci status register 2 (scs2) ? sci data register (scdr) ? sci baud rate register (scbr) 29-sci_d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sci MC68HC708XL36 264 sci motorola sci control register 1 sci control register 1: ? enables loop mode operation. ? enables the sci. ? controls output polarity. ? controls character length. ? controls sci wakeup method. ? controls idle character detection. ? enables parity function. ? controls parity type. loops loop mode select bit this read/write bit enables loop mode operation. in loop mode the rxd pin is disconnected from the sci, and the transmitter output goes into the receiver input. both the transmitter and the receiver must be enabled to use loop mode. reset clears the loops bit. 1 = loop mode enabled 0 = normal operation enabled ensci enable sci bit this read/write bit enables the sci and the sci baud rate generator. clearing ensci sets the scte and tc bits in sci status register 1 and disables transmitter interrupts. reset clears the ensci bit. 1 = sci enabled 0 = sci disabled address: $0013 bit 7 654321 bit 0 read: loops ensci txinv m wake illty pen pty write: reset: 00000000 figure 11. sci control register 1 (scc1) 30-sci_d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sci i/o registers MC68HC708XL36 motorola sci 265 txinv transmit inversion bit this read/write bit reverses the polarity of transmitted data. reset clears the txinv bit. 1 = transmitter output inverted 0 = transmitter output not inverted note: setting the txinv bit inverts all transmitted values, including idle, break, start, and stop bits. m mode (character length) bit this read/write bit determines whether sci characters are eight or nine bits long. (see table 8 .) the ninth bit can serve as an extra stop bit, as a receiver wakeup signal, or as a parity bit. reset clears the m bit. 1 = 9-bit sci characters 0 = 8-bit sci characters wake wakeup condition bit this read/write bit determines which condition wakes up the sci: a logic 1 (address mark) in the most significant bit position of a received character or an idle condition on the rxd pin. reset clears the wake bit. 1 = address mark wakeup 0 = idle line wakeup ilty idle line type bit this read/write bit determines when the sci starts counting logic 1s as idle character bits. the counting begins either after the start bit or after the stop bit. if the count begins after the start bit, then a string of logic 1s preceding the stop bit may cause false recognition of an idle character. beginning the count after the stop bit avoids false idle character recognition, but requires properly synchronized transmissions. reset clears the ilty bit. 1 = idle character bit count begins after stop bit 0 = idle character bit count begins after start bit 31-sci_d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sci MC68HC708XL36 266 sci motorola pen parity enable bit this read/write bit enables the sci parity function. (see table 8 .) when enabled, the parity function inserts a parity bit in the most significant bit position. (see figure 3 on page 241.) reset clears the pen bit. 1 = parity function enabled 0 = parity function disabled pty parity bit this read/write bit determines whether the sci generates and checks for odd parity or even parity. (see table 8 .) reset clears the pty bit. 1 = odd parity 0 = even parity note: changing the pty bit in the middle of a transmission or reception can generate a parity error. table 8. character format selection control bits character format m penCpty start bits data bits parity stop bits character length 0 0x 1 8 none 1 10 bits 1 0x 1 9 none 1 11 bits 0 10 1 7 even 1 10 bits 0 11 1 7 odd 1 10 bits 1 10 1 8 even 1 11 bits 1 11 1 8 odd 1 11 bits 32-sci_d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sci i/o registers MC68HC708XL36 motorola sci 267 sci control register 2 sci control register 2: ? enables the following cpu interrupt requests and dma service requests: C enables the scte bit to generate transmitter cpu interrupt requests or transmitter dma service requests. C enables the tc bit to generate transmitter cpu interrupt requests. C enables the scrf bit to generate receiver cpu interrupt requests or receiver dma service requests. C enables the idle bit to generate receiver cpu interrupt requests. ? enables the transmitter. ? enables the receiver. ? enables sci wakeup. ? transmits sci break characters. address: $0014 bit 7 654321 bit 0 read: sctie tcie scrie ilie te re rwu sbk write: reset: 00000000 figure 12. sci control register 2 (scc2) 33-sci_d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sci MC68HC708XL36 268 sci motorola sctie sci transmit interrupt enable bit this read/write bit enables the scte bit to generate sci transmitter cpu interrupt requests or dma service requests. setting the sctie bit and clearing the dma transfer enable bit, dmate, in scc3 enables the scte bit to generate cpu interrupt requests. setting both the sctie and dmate bits enables the scte bit to generate dma service requests. reset clears the sctie bit. 1 = scte enabled to generate cpu interrupt or dma service requests 0 = scte not enabled to generate cpu interrupt or dma service requests tcie transmission complete interrupt enable bit this read/write bit enables the tc bit to generate sci transmitter cpu interrupt requests. reset clears the tcie bit. 1 = tc enabled to generate cpu interrupt requests 0 = tc not enabled to generate cpu interrupt requests scrie sci receive interrupt enable bit this read/write bit enables the scrf bit to generate sci receiver cpu interrupt requests or sci receiver dma service requests. setting the scrie bit and clearing the dma receive enable bit, dmare, in scc3 enables the scrf bit to generate cpu interrupt requests. setting both scrie and dmare enables scrf to generate dma service requests. reset clears the scrie bit. 1 = scrf enabled to generate cpu interrupt or dma service requests 0 = scrf not enabled to generate cpu interrupt or dma service requests ilie idle line interrupt enable bit this read/write bit enables the idle bit to generate sci receiver cpu interrupt requests. reset clears the ilie bit. 1 = idle enabled to generate cpu interrupt requests 0 = idle not enabled to generate cpu interrupt requests 34-sci_d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sci i/o registers MC68HC708XL36 motorola sci 269 note: when sci receiver dma service requests are enabled (dmare = 1), then sci receiver cpu interrupt requests are disabled, and the state of the ilie bit has no effect. te transmitter enable bit setting this read/write bit begins the transmission by sending a preamble of 10 or 11 logic 1s from the transmit shift register to the txd pin. if software clears the te bit, the transmitter completes any transmission in progress before the txd returns to the idle condition (logic 1). clearing and then setting te during a transmission queues an idle character to be sent after the character currently being transmitted. reset clears the te bit. 1 = transmitter enabled 0 = transmitter disabled note: writing to the te bit is not allowed when the enable sci bit (ensci) is clear. ensci is in sci control register 1. re receiver enable bit setting this read/write bit enables the receiver. clearing the re bit disables the receiver but does not affect receiver interrupt flag bits. reset clears the re bit. 1 = receiver enabled 0 = receiver disabled note: writing to the re bit is not allowed when the enable sci bit (ensci) is clear. ensci is in sci control register 1. rwu receiver wakeup bit this read/write bit puts the receiver in a standby state during which receiver interrupts are disabled. the wake bit in scc1 determines whether an idle input or an address mark brings the receiver out of the standby state and clears the rwu bit. reset clears the rwu bit. 1 = standby state 0 = normal operation 35-sci_d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sci MC68HC708XL36 270 sci motorola sbk send break bit setting and then clearing this read/write bit transmits a break character followed by a logic 1. the logic 1 after the break character guarantees recognition of a valid start bit. if sbk remains set, the transmitter continuously transmits break characters with no logic 1s between them. reset clears the sbk bit. 1 = transmit break characters 0 = no break characters being transmitted note: do not toggle the sbk bit immediately after setting the scte bit. toggling sbk before the preamble begins causes the sci to send a break character instead of a preamble. sci control register 3 sci control register 3: ? stores the ninth sci data bit received and the ninth sci data bit to be transmitted. ? enables sci receiver full (scrf) dma service requests. ? enables sci transmitter empty (scte) dma service requests. ? enables the following interrupts: C receiver overrun interrupts C noise error interrupts C framing error interrupts C parity error interrupts address: $0015 bit 7 654321 bit 0 read: r8 t8 dmare dmate orie neie feie peie write: reset: u u 000000 = unimplemented u = unaffected figure 13. sci control register 3 (scc3) 36-sci_d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sci i/o registers MC68HC708XL36 motorola sci 271 r8 received bit 8 when the sci is receiving 9-bit characters, r8 is the read-only ninth bit (bit 8) of the received character. r8 is received at the same time that the scdr receives the other 8 bits. when the sci is receiving 8-bit characters, r8 is a copy of the eighth bit (bit 7). reset has no effect on the r8 bit. t8 transmitted bit 8 when the sci is transmitting 9-bit characters, t8 is the read/write ninth bit (bit 8) of the transmitted character. t8 is loaded into the transmit shift register at the same time that the scdr is loaded into the transmit shift register. reset has no effect on the t8 bit. dmare dma receive enable bit this read/write bit enables the dma to service sci receiver dma service requests generated by the scrf bit. setting the dmare bit disables sci receiver cpu interrupt requests. reset clears the dmare bit. 1 = dma enabled to service sci receiver dma service requests generated by the scrf bit (sci receiver cpu interrupt requests disabled) 0 = dma not enabled to service sci receiver dma service requests generated by the scrf bit (sci receiver cpu interrupt requests enabled) note: to enable the scrf bit to generate dma service requests, the sci receive interrupt enable bit (scrie) must be set. dmate dma transfer enable bit this read/write bit enables sci transmitter empty (scte) dma service requests. (see sci status register 1 on page 273.) setting the dmate bit disables scte cpu interrupt requests. reset clears dmate. 1 = scte dma service requests enabled scte cpu interrupt requests disabled 0 = scte dma service requests disabled scte cpu interrupt requests enabled 37-sci_d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sci MC68HC708XL36 272 sci motorola note: to enable the scte bit to generate dma service requests, the sci transmit interrupt enable bit (sctie) must be set. orie receiver overrun interrupt enable bit this read/write bit enables sci error cpu interrupt requests generated by the receiver overrun bit, or. 1 = sci error cpu interrupt requests from or bit enabled 0 = sci error cpu interrupt requests from or bit disabled neie receiver noise error interrupt enable bit this read/write bit enables sci error cpu interrupt requests generated by the noise error bit, ne. reset clears neie. 1 = sci error cpu interrupt requests from ne bit enabled 0 = sci error cpu interrupt requests from ne bit disabled feie receiver framing error interrupt enable bit this read/write bit enables sci error cpu interrupt requests generated by the framing error bit, fe. reset clears feie. 1 = sci error cpu interrupt requests from fe bit enabled 0 = sci error cpu interrupt requests from fe bit disabled peie receiver parity error interrupt enable bit this read/write bit enables sci receiver cpu interrupt requests generated by the parity error bit, pe. reset clears peie. 1 = sci error cpu interrupt requests from pe bit enabled 0 = sci error cpu interrupt requests from pe bit disabled 38-sci_d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sci i/o registers MC68HC708XL36 motorola sci 273 sci status register 1 sci status register 1 contains flags to signal the following conditions: ? transfer of scdr data to transmit shift register complete ? transmission complete ? transfer of receive shift register data to scdr complete ? receiver input idle ? receiver overrun ? noisy data ? framing error ? parity error scte sci transmitter empty bit this clearable, read-only bit is set when the scdr transfers a character to the transmit shift register. scte can generate an sci transmitter cpu interrupt request or an sci transmitter dma service request. when the sctie bit in scc2 is set and the dmate bit in scc3 is clear, scte generates an sci transmitter cpu interrupt request. with both the sctie and dmate bits set, scte generates an sci transmitter dma service request. in normal operation, clear the scte bit by reading scs1 with scte set and then writing to scdr. in dma transfers, the dma automatically clears the scte bit when it writes to the scdr. reset sets the scte bit. 1 = scdr data transferred to transmit shift register 0 = scdr data not transferred to transmit shift register address: $0016 bit 7 654321 bit 0 read: scte tc scrf idle or nf fe pe write: reset: 11000000 = unimplemented figure 14. sci status register 1 (scs1) 39-sci_d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sci MC68HC708XL36 274 sci motorola note: when dmate = 1, a write by the cpu to the sci data register can clear the scte bit inadvertently and cause the dma to miss a service request. note: setting the te bit for the first time also sets the scte bit. when enabling sci transmitter dma service requests, set the te bit after setting the dmate bit. otherwise setting the te and sctie bits generates an sci transmitter cpu interrupt request instead of a dma service request. tc transmission complete bit this read-only bit is set when the scte bit is set, and no data, preamble, or break character is being transmitted. tc generates an sci transmitter cpu interrupt request if the tcie bit in scc2 is also set. when the dma services an sci transmitter dma service request, the dma clears the tc bit by writing to the scdr. tc is cleared automatically when data, preamble, or break is queued and ready to be sent. there may be up to 1.5 transmitter clocks of latency between queueing data, preamble, and break and the transmission actually starting. reset sets the tc bit. 1 = no transmission in progress 0 = transmission in progress scrf sci receiver full bit this clearable, read-only bit is set when the data in the receive shift register transfers to the sci data register. scrf can generate an sci receiver cpu interrupt request or an sci receiver dma service request. when the scrie bit in scc2 is set and the dmare bit in scc3 is clear, scrf generates a cpu interrupt request. with both the scrie and dmare bits set, scrf generates a dma service request. in normal operation, clear the scrf bit by reading scs1 with scrf set and then reading the scdr. in dma transfers, the dma clears the scrf bit when it reads the scdr. reset clears scrf. 1 = received data available in scdr 0 = data not available in scdr note: when dmare = 1, a read by the cpu of the sci data register can clear the scrf bit inadvertently and cause the dma to miss a service request. 40-sci_d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sci i/o registers MC68HC708XL36 motorola sci 275 idle receiver idle bit this clearable, read-only bit is set when 10 or 11 consecutive logic 1s appear on the receiver input. idle generates an sci error cpu interrupt request if the ilie bit in scc2 is also set and the dmare bit in scc3 is clear. clear the idle bit by reading scs1 with idle set and then reading the scdr. after the receiver is enabled, it must receive a valid character that sets the scrf bit before an idle condition can set the idle bit. also, after the idle bit has been cleared, a valid character must again set the scrf bit before an idle condition can set the idle bit. reset clears the idle bit. 1 = receiver input idle 0 = receiver input active (or idle since the idle bit was cleared) or receiver overrun bit this clearable, read-only bit is set when software fails to read the scdr before the receive shift register receives the next character. the or bit generates an sci error cpu interrupt request if the orie bit in scc3 is also set. the data in the shift register is lost, but the data already in the scdr is not affected. clear the or bit by reading scs1 with or set and then reading the scdr. reset clears the or bit. 1 = receive shift register full and scrf = 1 0 = no receiver overrun software latency may allow an overrun to occur between reads of scs1 and scdr in the flag-clearing sequence. figure 15 shows the normal flag-clearing sequence and an example of an overrun caused by a delayed flag-clearing sequence. the delayed read of scdr does not clear the or bit because or was not set when scs1 was read. byte 2 caused the overrun and is lost. the next flag-clearing sequence reads byte 3 in the scdr instead of byte 2. in applications that are subject to software latency or in which it is important to know which byte is lost due to an overrun, the flag-clearing routine can check the or bit in a second read of scs1 after reading the data register. 41-sci_d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sci MC68HC708XL36 276 sci motorola figure 15. flag clearing sequence nf receiver noise flag bit this clearable, read-only bit is set when the sci detects noise on the rxd pin. nf generates an nf cpu interrupt request if the neie bit in scc3 is also set. clear the nf bit by reading scs1 and then reading the scdr. reset clears the nf bit. 1 = noise detected 0 = no noise detected fe receiver framing error bit this clearable, read-only bit is set when a logic 0 is accepted as the stop bit. fe generates an sci error cpu interrupt request if the feie bit in scc3 also is set. clear the fe bit by reading scs1 with fe set and then reading the scdr. reset clears the fe bit. 1 = framing error detected 0 = no framing error detected byte 1 normal flag clearing sequence read scs1 scrf = 1 read scdr byte 1 scrf = 1 scrf = 1 byte 2 byte 3 byte 4 or = 0 read scs1 scrf = 1 or = 0 read scdr byte 2 scrf = 0 read scs1 scrf = 1 or = 0 scrf = 1 scrf = 0 read scdr byte 3 scrf = 0 byte 1 read scs1 scrf = 1 read scdr byte 1 scrf = 1 scrf = 1 byte 2 byte 3 byte 4 or = 0 read scs1 scrf = 1 or = 1 read scdr byte 3 delayed flag clearing sequence or = 1 scrf = 1 or = 1 scrf = 0 or = 1 scrf = 0 or = 0 42-sci_d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sci i/o registers MC68HC708XL36 motorola sci 277 pe receiver parity error bit this clearable, read-only bit is set when the sci detects a parity error in incoming data. pe generates a pe cpu interrupt request if the peie bit in scc3 is also set. clear the pe bit by reading scs1 with pe set and then reading the scdr. reset clears the pe bit. 1 = parity error detected 0 = no parity error detected sci status register 2 sci status register 2 contains flags to signal the following conditions: ? break character detected ? incoming data bkf break flag bit this clearable, read-only bit is set when the sci detects a break character on the rxd pin. in scs1, the fe and scrf bits are also set. in 9-bit character transmissions, the r8 bit in scc3 is cleared. bkf does not generate a cpu interrupt request or a dma service request. clear bkf by reading scs2 with bkf set and then reading the scdr. once cleared, bkf can become set again only after logic 1s again appear on the rxd pin followed by another break character. reset clears the bkf bit. 1 = break character detected 0 = no break character detected address: $0017 bit 7 654321 bit 0 read: bkf rpf write: reset: 00000000 = unimplemented figure 16. sci status register 2 (scs2) 43-sci_d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sci MC68HC708XL36 278 sci motorola rpf reception in progress flag bit this read-only bit is set when the receiver detects a logic 0 during the rt1 time period of the start bit search. rpf does not generate an interrupt request. rpf is reset after the receiver detects false start bits (usually from noise or a baud rate mismatch), or when the receiver detects an idle character. polling rpf before disabling the sci module or entering stop mode can show whether a reception is in progress. 1 = reception in progress 0 = no reception in progress sci data register the sci data register is the buffer between the internal data bus and the receive and transmit shift registers. reset has no effect on data in the sci data register. r7/t7Cr0/t0 receive/transmit data bits reading address $0018 accesses the read-only received data bits, r7Cr0. writing to address $0018 writes the data to be transmitted, t7Ct0. reset has no effect on the sci data register. note: do not use read-modify-write instructions on the sci data register. address: $0018 bit 7 654321 bit 0 read: r7 r6 r5 r4 r3 r2 r1 r0 write: t7 t6 t5 t4 t3 t2 t1 t0 reset: unaffected by reset figure 17. sci data register (scdr) 44-sci_d f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sci i/o registers MC68HC708XL36 motorola sci 279 sci baud rate register the baud rate register selects the baud rate for both the receiver and the transmitter. scp1 and scp0 sci baud rate prescaler bits these read/write bits select the baud rate prescaler divisor as shown in table 9 . reset clears scp1 and scp0. address: $0019 bit 7 654321 bit 0 read: scp1 scp0 r scr2 scr1 scr0 write: reset: 00000000 = unimplemented r = reserved figure 18. sci baud rate register (scbr) table 9. sci baud rate prescaling scp[1:0] prescaler divisor (pd) 00 1 01 3 10 4 11 13 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sci MC68HC708XL36 280 sci motorola scr2Cscr0 sci baud rate select bits these read/write bits select the sci baud rate divisor as shown in table 10 . reset clears scr2Cscr0. use the following formula to calculate the sci baud rate: where: f crystal = crystal frequency pd = prescaler divisor bd = baud rate divisor table 10. sci baud rate selection scr[2:1:0] baud rate divisor (bd) 000 1 001 2 010 4 011 8 100 16 101 32 110 64 111 128 baud rate f crystal 64 pd bd ------------------------------------ = f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sci i/o registers MC68HC708XL36 motorola sci 281 table 11 shows the sci baud rates that can be generated with a 4.9152-mhz crystal. table 11. sci baud rate selection examples scp[1:0] prescaler divisor (pd) scr[2:1:0] baud rate divisor (bd) baud rate (f crystal = 4.9152 mhz) 00 1 000 1 76,800 00 1 001 2 38,400 00 1 010 4 19,200 00 1 011 8 9600 00 1 100 16 4800 00 1 101 32 2400 00 1 110 64 1200 00 1 111 128 600 01 3 000 1 25,600 01 3 001 2 12,800 01 3 010 4 6400 01 3 011 8 3200 01 3 100 16 1600 01 3 101 32 800 01 3 110 64 400 01 3 111 128 200 10 4 000 1 19,200 10 4 001 2 9600 10 4 010 4 4800 10 4 011 8 2400 10 4 100 16 1200 10 4 101 32 600 10 4 110 64 300 10 4 111 128 150 11 13 000 1 5908 11 13 001 2 2954 11 13 010 4 1477 11 13 011 8 739 11 13 100 16 369 11 13 101 32 185 11 13 110 64 92 11 13 111 128 46 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . sci MC68HC708XL36 282 sci motorola f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC708XL36 motorola i/o ports 283 input/output ports i/o ports contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .284 port a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286 port a data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286 data direction register a . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .286 port b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .288 port b data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .288 data direction register b . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .288 port c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290 port c data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290 data direction register c . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .290 port d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292 port d data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292 data direction register d . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .292 port e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .294 port e data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .294 data direction register e . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .296 port f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297 port f data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .297 data direction register f . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .299 port g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300 port g data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .300 data direction register g . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .301 port h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303 port h data register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303 data direction register h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .303 1-ports_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . i/o ports MC68HC708XL36 284 i/o ports motorola introduction fifty-four bidirectional input-output (i/o) pins form eight parallel ports. all i/o pins are programmable as inputs or outputs. note: connect any unused i/o pins to an appropriate logic level, either v dd or v ss . although the i/o ports do not require termination for proper operation, termination reduces excess current consumption and the possibility of electrostatic damage. register name bit 7 654321 bit 0 port a data register (porta) read: pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 write: reset: unaffected by reset port b data register (portb) read: pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 write: reset: unaffected by reset port c data register (portc) read: pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 write: reset: unaffected by reset port d data register (portd) read: pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 write: reset: unaffected by reset data direction register a (ddra) read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset: 00000000 data direction register b (ddrb) read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset: 00000000 data direction register c (ddrc) read: ddrc7 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc1 ddrc0 write: reset: 00000000 data direction register d (ddrd) read: ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset: 00000000 port e data register (porte) read: pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 write: reset: unaffected by reset port f data register (portf) read: 0 0 pf5 pf4 pf3 pf2 pf1 pf0 write: reset: unaffected by reset = unimplemented figure 1. i/o register summary 2-ports_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . i/o ports introduction MC68HC708XL36 motorola i/o ports 285 port g data register (portg) read: 0000 pg3 pg2 pg1 pg0 write: reset: unaffected by reset port h data register (porth) read: 0000 ph3 ph2 ph1 ph0 write: reset: unaffected by reset data direction register e (ddre) read: ddre7 ddre6 ddre5 ddre4 ddre3 ddre2 ddre1 ddre0 write: reset: 00000000 data direction register f (ddrf) read: 0 0 ddrf5 ddrf4 ddrf3 ddrf2 ddrf1 ddrf0 write: reset: 00000000 data direction register g (ddrg) read: 0000 ddrg3 ddrg2 ddrg1 ddrg0 write: reset: 00000000 data direction register h (ddrh) read: 0000 ddrh3 ddrh2 ddrh1 ddrh0 write: reset: 00000000 table 1. i/o register address summary register porta portb portc portd ddra ddrb ddrc ddrd porte portf address $0000 $0001 $0002 $0003 $0004 $0005 $0006 $0007 $0008 $0009 register portg porth ddre ddrf ddrg ddrh address $000a $000b $000c $000d $000e $000f register name bit 7 654321 bit 0 = unimplemented figure 1. i/o register summary 3-ports_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . i/o ports MC68HC708XL36 286 i/o ports motorola port a port a is an 8-bit, general-purpose bidirectional i/o port. port a data register porta contains the data latches for the eight port a pins. pa[7:0] port a data bits these read/write bits are software programmable. data direction of each port a pin is under the control of the corresponding bit in data direction register a. reset has no effect on port a data. data direction register a data direction register a determines whether each port a pin is an input or an output. writing a logic 1 to a ddra bit enables the output buffer for the corresponding port a pin; a logic 0 disables the output buffer. address: $0000 bit 7 654321 bit 0 read: pa7 pa6 pa5 pa4 pa3 pa2 pa1 pa0 write: reset: unaffected by reset figure 2. port a data register (porta) address: $0004 bit 7 654321 bit 0 read: ddra7 ddra6 ddra5 ddra4 ddra3 ddra2 ddra1 ddra0 write: reset: 00000000 figure 3. data direction register a (ddra) 4-ports_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . i/o ports port a MC68HC708XL36 motorola i/o ports 287 ddra[7:0] data direction register a bits these read/write bits control port a data direction. reset clears ddra[7:0], configuring all port a pins as inputs. 1 = corresponding port a pin configured as output 0 = corresponding port a pin configured as input note: avoid glitches on port a pins by writing to the port a data register before changing data direction register a bits from 0 to 1. figure 4 shows the port a i/o logic. figure 4. port a i/o circuit when bit ddrax is a logic 1, reading address $0000 reads the pax data latch. when bit ddrax is a logic 0, reading address $0000 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 2 summarizes the operation of the port a pins. 1. writing affects data register, but does not affect input. table 2. port a pin operation data direction bit i/o pin mode access to data bit read write 0 input, high-impedance pin latch (1) 1 output latch latch read ddra ($0004) write ddra ($0004) reset write porta ($0000) read porta ($0000) pax ddrax pax internal data bus 5-ports_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . i/o ports MC68HC708XL36 288 i/o ports motorola port b port b is an 8-bit, general-purpose bidirectional i/o port. port b data register portb contains the data latches for the eight port b pins. pb[7:0] port b data bits these read/write bits are software-programmable. data direction of each port b pin is under the control of the corresponding bit in data direction register b. reset has no effect on port b data. data direction register b data direction register b determines whether each port b pin is an input or an output. writing a logic 1 to a ddrb bit enables the output buffer for the corresponding port b pin; a logic 0 disables the output buffer. address: $0001 bit 7 654321 bit 0 read: pb7 pb6 pb5 pb4 pb3 pb2 pb1 pb0 write: reset: unaffected by reset figure 5. port b data register (portb) address: $0005 bit 7 654321 bit 0 read: ddrb7 ddrb6 ddrb5 ddrb4 ddrb3 ddrb2 ddrb1 ddrb0 write: reset: 00000000 figure 6. data direction register b (ddrb) 6-ports_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . i/o ports port b MC68HC708XL36 motorola i/o ports 289 ddrb[7:0] data direction register b bits these read/write bits control port b data direction. reset clears ddrb[7:0], configuring all port b pins as inputs. 1 = corresponding port b pin configured as output 0 = corresponding port b pin configured as input note: avoid glitches on port b pins by writing to the port b data register before changing data direction register b bits from 0 to 1. figure 7 shows the port b i/o logic. figure 7. port b i/o circuit when bit ddrbx is a logic 1, reading address $0001 reads the pbx data latch. when bit ddrbx is a logic 0, reading address $0001 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 3 summarizes the operation of the port b pins. 1. writing affects data register, but does not affect input. table 3. port b pin operation data direction bit i/o pin mode access to data bit read write 0 input, high-impedance pin latch (1) 1 output latch latch read ddrb ($0005) write ddrb ($0005) reset write portb ($0001) read portb ($0001) pbx ddrbx pbx internal data bus 7-ports_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . i/o ports MC68HC708XL36 290 i/o ports motorola port c port c is an 8-bit, general-purpose bidirectional i/o port. port c data register portc contains the data latches for the eight port c pins. pc[7:0] port c data bits these read/write bits are software-programmable. data direction of each port c pin is under the control of the corresponding bit in data direction register c. reset has no effect on port c data. data direction register c data direction register c determines whether each port c pin is an input or an output. writing a logic 1 to a ddrc bit enables the output buffer for the corresponding port c pin; a logic 0 disables the output buffer. address: $0002 bit 7 654321 bit 0 read: pc7 pc6 pc5 pc4 pc3 pc2 pc1 pc0 write: reset: unaffected by reset figure 8. port c data register (portc) address: $0006 bit 7 654321 bit 0 read: ddrc7 ddrc6 ddrc5 ddrc4 ddrc3 ddrc2 ddrc ddrc0 write: reset: 00000000 figure 9. data direction register c (ddrc) 8-ports_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . i/o ports port c MC68HC708XL36 motorola i/o ports 291 ddrc[7:0] data direction register c bits these read/write bits control port c data direction. reset clears ddrc[7:0], configuring all port c pins as inputs. 1 = corresponding port c pin configured as output 0 = corresponding port c pin configured as input note: avoid glitches on port c pins by writing to the port c data register before changing data direction register c bits from 0 to 1. figure 10 shows the port c i/o logic. figure 10. port c i/o circuit when bit ddrcx is a logic 1, reading address $0002 reads the pcx data latch. when bit ddrcx is a logic 0, reading address $0002 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 4 summarizes the operation of the port c pins. 1. writing affects data register, but does not affect input. table 4. port c pin operation data direction bit i/o pin mode access to data bit read write 0 input, high-impedance pin latch (1) 1 output latch latch read ddrc ($0006) write ddrc ($0006) reset write portc ($0002) read portc ($0002) pcx ddrcx pcx internal data bus 9-ports_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . i/o ports MC68HC708XL36 292 i/o ports motorola port d port d is an 8-bit, general-purpose i/o port. port d data register portd contains the data latches for the eight port d pins. pd[7:0] port d data bits these read/write bits are software-programmable. data direction of each port d pin is under the control of the corresponding bit in data direction register d. reset has no effect on port d data. the keyboard interrupt enable bits, kbie[7:0], in the keyboard interrupt control register (kbicr), enable the port d pins as external interrupt pins. (see external interrupt module on page 311.) data direction register d data direction register d determines whether each port d pin is an input or an output. writing a logic 1 to a ddrd bit enables the output buffer for the corresponding port d pin; a logic 0 disables the output buffer. address: $0003 bit 7 654321 bit 0 read: pd7 pd6 pd5 pd4 pd3 pd2 pd1 pd0 write: reset: unaffected by reset figure 11. port d data register (portd) address: $0007 bit 7 654321 bit 0 read: ddrd7 ddrd6 ddrd5 ddrd4 ddrd3 ddrd2 ddrd1 ddrd0 write: reset: 00000000 figure 12. data direction register d (ddrd) 10-ports_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . i/o ports port d MC68HC708XL36 motorola i/o ports 293 ddrd[7:0] data direction register d bits these read/write bits control port d data direction. reset clears ddrd[7:0], configuring all port d pins as inputs. 1 = corresponding port d pin configured as output 0 = corresponding port d pin configured as input note: avoid glitches on port d pins by writing to the port d data register before changing data direction register d bits from 0 to 1. figure 13 shows the port d i/o logic. figure 13. port d i/o circuit when bit ddrdx is a logic 1, reading address $0003 reads the pdx data latch. when bit ddrdx is a logic 0, reading address $0003 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 5 summarizes the operation of the port d pins. 1. writing affects data register, but does not affect input. table 5. port d pin operation data direction bit i/o pin mode access to data bit read write 0 input, high-impedance pin latch (1) 1 output latch latch read ddrd ($0007) write ddrd ($0007) reset write portd ($0003) read portd ($0003) pdx ddrdx pdx internal data bus 11-ports_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . i/o ports MC68HC708XL36 294 i/o ports motorola port e port e is an 8-bit special function port that shares five of its pins with the timer interface module (tim) and two of its pins with the serial communications interface module (sci). port e data register porte contains the data latches for the eight port e pins. pe[7:0] port e data bits pe[7:0] are read/write, software programmable bits. data direction of each port e pin is under the control of the corresponding bit in data direction register e. tch[3:0] timer channel i/o bits the pe7/tch3Cpe4/tch0 pins are the tim input capture/output compare pins. the edge/level select bits, elsxb:elsxa, determine whether the pe7/tch3Cpe4/tch0 pins are timer channel i/o pins or general-purpose i/o pins. (see timer interface module on page 171.) note: data direction register e (ddre) does not affect the data direction of port e pins that are being used by the tim. however, the ddre bits always determine whether reading port e returns the states of the latches or the states of the pins. (see table 6 .) address: $0008 bit 7 654321 bit 0 read: pe7 pe6 pe5 pe4 pe3 pe2 pe1 pe0 write: reset: unaffected by reset alternate function: tch3 tch2 tch1 tch0 tclk txd rxd figure 14. port e data register (porte) 12-ports_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . i/o ports port e MC68HC708XL36 motorola i/o ports 295 tclk timer clock input the pe3/tclk pin is the external clock input for the tim. the prescaler select bits, ps[2:0], select pe3/tclk as the tim clock input. (see timer interface module on page 171.) when not selected as the tim clock, pe3/tclk is available for general-purpose i/o. txd sci transmit data output the pe2/txd pin is the transmit data output for the sci module. when the enable sci bit, ensci, is clear, the sci module is disabled and the pe2/txd pin is available for general-purpose i/o. (see serial communications interface module on page 235.) note: data direction register e (ddre) does not affect the data direction of port e pins that are being used by the sci module. however, the ddre bits always determine whether reading port e returns the states of the latches or the states of the pins. (see table 6 .) rxd sci receive data input the pe1/rxd pin is the receive data input for the sci module. when the enable sci bit, ensci, is clear, the sci module is disabled and the pe1/rxd pin is available for general-purpose i/o. (see serial communications interface module on page 235.) 13-ports_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . i/o ports MC68HC708XL36 296 i/o ports motorola data direction register e data direction register e determines whether each port e pin is an input or an output. writing a logic 1 to a ddre bit enables the output buffer for the corresponding port e pin; a logic 0 disables the output buffer. ddre[7:0] data direction register e bits these read/write bits control port e data direction. reset clears ddre[7:0], configuring all port e pins as inputs. 1 = corresponding port e pin configured as output 0 = corresponding port e pin configured as input note: avoid glitches on port e pins by writing to the port e data register before changing data direction register e bits from 0 to 1. figure 16 shows the port e i/o logic. figure 16. port e i/o circuit address: $000c bit 7 654321 bit 0 read: ddr37 ddre6 ddre5 ddre4 ddre3 ddre2 ddte1 ddre0 write: reset: 00000000 figure 15. data direction register e (ddre) read ddre ($000c) write ddre ($000c) reset write porte ($0008) read porte ($0008) pex ddrex pex internal data bus 14-ports_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . i/o ports port f MC68HC708XL36 motorola i/o ports 297 when bit ddrex is a logic 1, reading address $0008 reads the pex data latch. when bit ddrex is a logic 0, reading address $0008 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 6 summarizes the operation of the port e pins. 1. writing affects data register, but does not affect input. port f portf is a 6-bit, special function port that shares four of its pins with the serial peripheral interface module (spi). port f data register portf contains the data latches for the six port f pins. table 6. port e pin operation data direction bit i/o pin mode access to data bit read write 0 input, high-impedance pin latch (1) 1 output latch latch address: $0009 bit 7 654321 bit 0 read: 0 0 pf5 pf4 pf3 pf2 pf1 pf0 write: reset: unaffected by reset alternate function: miso mosi spsck ss = unimplemented figure 17. port f data register (portf) 15-ports_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . i/o ports MC68HC708XL36 298 i/o ports motorola pf[5:0] port f data bits these read/write bits are software programmable. data direction of each port f pin is under the control of the corresponding bit in data direction register f. reset has no effect on pf[5:0]. miso master in/slave out the pf3/miso pin is the master in/slave out terminal of the spi module. when the spi enable bit, spe, is clear, the spi module is disabled and the pf3/miso pin is available for general-purpose i/o. (see serial peripheral interface module on page 201.) note: data direction register f (ddrf) does not affect the data direction of port f pins that are being used by the spi module. however, the ddrf bits always determine whether reading port f returns the states of the latches or the states of the pins. (see table 7 .) mosi master out/slave in the pf2/mosi pin is the master out/slave in terminal of the spi module. when the spe bit is clear, the ppf2/mosi pin is available for general-purpose i/o. (see serial peripheral interface module on page 201.) spsck spi serial clock the pf1/spsck pin is the serial clock input of the spi module. when the spe bit is clear, the pf1/spsck pin is available for general-purpose i/o. ss slave select the pf0/ ss pin is the slave select input of the spi module. when the spe bit is clear or when the spi master bit, spmstr, is set, the pf0/ ss pin is available for general-purpose i/o. (see serial peripheral interface module on page 201.) when the spi is enabled, the ddrf0 bit in data direction register f (ddrf) has no effect on the pf0/ ss pin. 16-ports_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . i/o ports port f MC68HC708XL36 motorola i/o ports 299 data direction register f data direction register f determines whether each port f pin is an input or an output. writing a logic 1 to a ddrf bit enables the output buffer for the corresponding port f pin; a logic 0 disables the output buffer. ddrf[5:0] data direction register f bits these read/write bits control port f data direction. reset clears ddrf[5:0], configuring all port f pins as inputs. 1 = corresponding port f pin configured as output 0 = corresponding port f pin configured as input note: avoid glitches on port f pins by writing to the port f data register before changing data direction register f bits from 0 to 1. figure 19 shows the port f i/o logic. figure 19. port f i/o circuit address: $000d bit 7 654321 bit 0 read: ddrf5 ddrf4 ddrf3 ddrf2 ddrf1 ddrf0 write: reset: 00000000 = unimplemented figure 18. data direction register f (ddrf) read ddrf ($000d) write ddrf ($000d) reset write portf ($0009) read portf ($0009) pfx ddrfx pfx internal data bus 17-ports_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . i/o ports MC68HC708XL36 300 i/o ports motorola when bit ddrfx is a logic 1, reading address $0009 reads the pfx data latch. when bit ddrfx is a logic 0, reading address $0009 reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 7 summarizes the operation of the port f pins. 1. writing affects data register, but does not affect input. port g port g is a 4-bit, general-purpose bidirectional i/o port. note: port g is available only on the 64-pin qfp. port g data register portg contains the data latches for the four port g pins. table 7. port f pin operation data direction bit i/o pin mode access to data bit read write 0 input, high-impedance pin latch] (1) 1 output latch latch address: $000a bit 7 654321 bit 0 read: 0000 pg3 pg2 pg1 pg0 write: reset: unaffected by reset = unimplemented figure 20. port g data register (portg) 18-ports_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . i/o ports port g MC68HC708XL36 motorola i/o ports 301 pg[3:0] port g data bits these read/write bits are software-programmable. data direction of each bit is under the control of the corresponding bit in data direction register g. reset has no effect on port g data. data direction register g data direction register g determines whether each port g pin is an input or an output. writing a logic 1 to a ddrg bit enables the output buffer for the corresponding port g pin; a logic 0 disables the output buffer. ddrg[3:0] data direction register g bits these read/write bits control port g data direction. reset clears ddrg[3:0], configuring all port g pins as inputs. 1 = corresponding port g pin configured as output 0 = corresponding port g pin configured as input note: avoid glitches on port g pins by writing to the port g data register before changing data direction register g bits from 0 to 1. figure 22 shows the port g i/o logic. address: $000e bit 7 654321 bit 0 read: 0000 ddrg3 ddrg2 ddrg1 ddrg0 write: reset: 00000000 = unimplemented figure 21. data direction register g (ddrg) 19-ports_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . i/o ports MC68HC708XL36 302 i/o ports motorola figure 22. port g i/o circuit when bit ddrgx is a logic 1, reading address $000a reads the pgx data latch. when bit ddrgx is a logic 0, reading address $000a reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 8 summarizes the operation of the port g pins. 1. writing affects data register, but does not affect input. table 8. port g pin operation data direction bit i/o pin mode access to data bit read write 0 input, high-impedance pin latch] (1) 1 output latch latch read ddrg ($000e) write ddrg ($000e) reset write portg ($000a) read portg ($000a) pgx ddrgx pgx internal data bus 20-ports_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . i/o ports port h MC68HC708XL36 motorola i/o ports 303 port h port h is a 4-bit, general-purpose bidirectional i/o port. note: port h is available only on the 64-pin qfp. port h data register porth contains the latches for the four port h pins. ph[3:0] port h data bits these read/write bits are software programmable. data direction of each bit is under the control of the corresponding bit in data direction register h. reset has no effect on port h data. data direction register h data direction register h determines whether each port h pin is an input or an output. writing a logic 1 to a ddrh bit enables the output buffer for the corresponding port h pin; a logic 0 disables the output buffer. address: $000b bit 7 654321 bit 0 read: 0000 ph3 ph2 ph1 ph0 write: reset: unaffected by reset = unimplemented figure 23. port h data register (porth) address: $000f bit 7 654321 bit 0 read: 0000 ddrh3 ddrh2 ddrh1 ddrh0 write: reset: 00000000 = unimplemented figure 24. data direction register h (ddrh) 21-ports_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . i/o ports MC68HC708XL36 304 i/o ports motorola ddrh[3:0] data direction register h bits these read/write bits control port h data direction. reset clears ddr[3:0], configuring all port h pins as inputs. 1 = corresponding port h pin configured as output 0 = corresponding port h pin configured as input note: avoid glitches on port h pins by writing to the port h data register before changing the data direction register h bits from 0 to 1. figure 25 shows the port h i/o logic. figure 25. port h i/o circuit when bit ddrhx is a logic 1, reading address $000b reads the phx data latch. when bit ddrhx is a logic 0, reading address $000b reads the voltage level on the pin. the data latch can always be written, regardless of the state of its data direction bit. table 9 summarizes the operation of the port h pins. 1. writing affects data register, but does not affect input. table 9. port h pin operation data direction bit i/o pin mode access to data bit read write 0 input, high-impedance pin latch (1) 1 output latch latch read ddrh ($000f) write ddrh ($000f) reset write porth ($000b) read porth ($000b) phx ddrhx phx internal data bus 22-ports_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC708XL36 motorola cop 305 computer operating properly module cop contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .305 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .306 i/o signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307 cgmxclk . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307 stop instruction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307 copctl write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .307 internal reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308 reset vector fetch . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308 copd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308 coprs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308 cop control register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .308 interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309 monitor mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309 low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309 stop mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .309 cop module during break interrupts . . . . . . . . . . . . . . . . . . . . . . . .310 introduction the cop module contains a free-running counter that generates a reset if allowed to overflow. the cop module helps software recover from runaway code. prevent a cop reset by periodically clearing the cop counter. 1-copopt2_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . cop MC68HC708XL36 306 cop motorola functional description figure 1. cop block diagram the cop counter is a free-running 6-bit counter preceded by a 12-bit prescaler. if not cleared by software, the cop counter overflows and generates an asynchronous reset after 2 13 C2 4 or 2 18 C2 4 cgmxclk cycles, depending on the state of the cop rate select bit, coprs, in the configuration register. when coprs = 0, a 4.9152-mhz crystal gives a cop timeout period of 53.3 ms. writing any value to location $ffff before an overflow occurs prevents a cop reset by clearing the cop counter and stages 5 through 12 of the prescaler. copctl write cgmxclk reset vector fetch reset reset status internal reset sources stop instruction clear stages 5C12 clear all stages 6-bit cop counter copd from config reset copctl write clear cop counter coprs from config 12-bit cop prescaler register 2-copopt2_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . cop i/o signals MC68HC708XL36 motorola cop 307 note: service the cop immediately after reset and before entering or after exiting stop mode to guarantee the maximum time before the first cop counter overflow. a cop reset pulls the rst pin low for 32 cgmxclk cycles and sets the cop bit in the reset status register (rsr). in monitor mode, the cop is disabled if the rst pin or the irq pin is held at v dd +v hi . during the break state, v dd +v hi on the rst pin disables the cop. note: place cop clearing instructions in the main program and not in an interrupt subroutine. such an interrupt subroutine could keep the cop from generating a reset even while the main program is not working properly. i/o signals the following paragraphs describe the signals shown in figure 1 . cgmxclk cgmxclk is the crystal oscillator output signal. cgmxclk frequency is equal to the crystal frequency. stop instruction the stop instruction clears the cop prescaler. copctl write writing any value to the cop control register (copctl) (see cop control register on page 308) clears the cop counter and clears stages 12 through 5 of the cop prescaler. reading the cop control register returns the reset vector. power-on reset the power-on reset (por) circuit clears the cop prescaler 4096 cgmxclk cycles after power-up. 3-copopt2_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . cop MC68HC708XL36 308 cop motorola internal reset an internal reset clears the cop prescaler and the cop counter. reset vector fetch a reset vector fetch occurs when the vector address appears on the data bus. a reset vector fetch clears the cop prescaler. copd the copd signal reflects the state of the cop disable bit (copd) in the configuration register. (see configuration register on page 39.) coprs the coprs signal reflects the state of the cop rate select bit. cop control register the cop control register is located at address $ffff and overlaps the reset vector. writing any value to $ffff clears the cop counter and starts a new timeout period. reading location $ffff returns the low byte of the reset vector. address: $ffff bit 7 654321 bit 0 read: low byte of reset vector write: clear cop counter reset: unaffected by reset figure 2. cop control register (copctl) 4-copopt2_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . cop interrupts MC68HC708XL36 motorola cop 309 interrupts the cop does not generate cpu interrupt requests or dma service requests. monitor mode the cop is disabled in monitor mode when v dd +v hi is present on the irq1/v pp pin or on the rst pin. low-power modes the wait and stop instructions put the mcu in low-power-consump- tion standby modes. wait mode the cop remains active in wait mode. to prevent a cop reset during wait mode, periodically clear the cop counter in a cpu interrupt routine or a dma service routine. stop mode stop mode turns off the cgmxclk input to the cop and clears the cop prescaler. service the cop immediately before entering or after exiting stop mode to ensure a full cop timeout period after entering or exiting stop mode. the stop bit in the configuration register (config) enables the stop instruction. to prevent inadvertently turning off the cop with a stop instruction, disable the stop instruction by clearing the stop bit. 5-copopt2_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . cop MC68HC708XL36 310 cop motorola cop module during break interrupts the cop is disabled during a break interrupt when v dd +v hi is present on the rst pin. 6-copopt2_b f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC708XL36 motorola irq 311 external interrupt module irq contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .311 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .312 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .312 irq1 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .314 irq2 pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .316 low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317 stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .317 irq module during break interrupts . . . . . . . . . . . . . . . . . . . . . . . . .318 irq status and control register . . . . . . . . . . . . . . . . . . . . . . . . . . . .318 introduction the irq module provides two independently maskable external interrupt pins. 1-intirq2_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . irq MC68HC708XL36 312 irq motorola features features of the irq module include the following: ? two dedicated external interrupt pins with separate external interrupt masks ? hysteresis buffers ? programmable edge-only or edge- and level- interrupt sensitivity ? automatic interrupt acknowledge ? exit from low-power modes functional description a logic 0 applied to any of the external interrupt pins can latch a cpu interrupt request. figure 1 shows the structure of the irq module. interrupt signals on the irq1 pin are latched separately from interrupt signals on the irq2 pin. cpu interrupt requests remain latched until one of the following actions occurs: ? vector fetch a vector fetch automatically generates an interrupt acknowledge signal that clears the cpu interrupt request that caused the vector fetch. ? software clear software can clear a latched cpu interrupt request by writing to the appropriate acknowledge bit in the interrupt status and control register (iscr). writing a logic 1 to the ack1 bit clears the irq1 cpu interrupt request. writing a logic 1 to the ack2 bit clears the irq2 cpu interrupt request. ? reset a reset automatically clears both irq1 and irq2 cpu interrupt requests. all of the external interrupt pins are falling-edge-triggered and are software-configurable to be both falling-edge and low-level-triggered. the mode1 bit in the iscr controls the triggering sensitivity of the irq1 pin. the mode2 bit controls the triggering sensitivity of the irq2 pin. 2-intirq2_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC708XL36 motorola irq 313 irq functional description figure 1. irq module block diagram imask1 dq ck clr irq1 cpu interrupt irq1 ff request v dd mode1 synchro- nizer irq1f imask2 dq ck clr irq2 cpu interrupt irq2 ff request v dd mode2 synchro- nizer irq2f to cpu for bil/bih instructions vector fetch decoder internal address bus reset ack1 irq2 vector fetch decoder reset ack1 irq1 3-intirq2_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . irq MC68HC708XL36 314 irq motorola when an interrupt pin is edge-triggered only, the cpu interrupt request remains latched until a vector fetch, software clear, or reset occurs. when an interrupt pin is both falling-edge and low-level-triggered, the cpu interrupt request remains latched until both of the following occur: ? vector fetch or software clear ? return of the interrupt pin to logic 1 the vector fetch or software clear can occur before or after the interrupt pin returns to logic 1. as long as the pin is low, the cpu interrupt request remains pending. a reset clears the cpu interrupt request and the modex control bit even if the pin stays low. when set, the imask1 and imask2 bits in the iscr mask all external interrupt requests. a latched cpu interrupt request is not presented to the interrupt priority logic unless the corresponding imask bit is clear. note: the interrupt mask (i) in the condition code register (ccr) masks all cpu interrupt requests, including external interrupt requests. irq1 pin a logic 0 on the irq1 pin can latch a cpu interrupt request. a vector fetch, software clear, or reset clears the irq1 cpu interrupt request. if the mode1 bit is set, the irq1 pin is both falling-edge-sensitive and low-level-sensitive. with mode1 set, both of the following actions must occur to clear the irq1 cpu interrupt request: ? vector fetch, software clear, or reset a vector fetch generates an interrupt acknowledge signal to clear the cpu interrupt request. software can generate the interrupt acknowledge signal by writing a logic 1 to the ack1 bit in the interrupt status and control register (iscr). the ack1 bit is useful in applications that poll the irq1 pin and require software to clear the irq1 cpu interrupt request. writing to the ack1 bit before leaving an interrupt service routine can also prevent spurious interrupts due to noise. setting ack1 does not affect subsequent transitions on the irq1 pin. a falling edge that occurs after writing to the ack1 4-intirq2_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . irq functional description MC68HC708XL36 motorola irq 315 bit latches another cpu interrupt request. if the irq1 mask bit, imask1, is clear, the cpu loads the program counter with the vector address at locations $fffa and $fffb. ? return of the irq1 pin to logic 1 as long as the irq1 pin is at logic 0, the irq1 cpu interrupt request remains latched. the vector fetch, software clear, or reset and the return of the irq1 pin to logic 1 can occur in any order. a reset clears the cpu interrupt request and the mode1 bit, clearing the cpu interrupt request even if the pin stays low. if the mode1 bit is clear, the irq1 pin is falling-edge-sensitive only. with mode1 clear, a vector fetch or software clear immediately clears the irq1 cpu interrupt request. the irqf1 bit in the iscr register can be used to check for pending cpu interrupts. the irqf1 bit is not affected by the imask1 bit, which makes it useful in applications where polling is preferred. use the bih or bil instruction to read the logic level on the irq1 pin. note: to avoid spurious cpu interrupts caused by noise, mask cpu interrupt requests in the interrupt routine when using the level-sensitive interrupt trigger. 5-intirq2_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . irq MC68HC708XL36 316 irq motorola irq2 pin a logic 0 on the irq2 pin can latch a cpu interrupt request. a vector fetch, software clear, or reset clears the irq2 cpu interrupt request. if the mode2 bit is set, the irq2 pin is both falling-edge-sensitive and low-level-sensitive. with mode2 set, both of the following actions must occur to clear an irq2 cpu interrupt request: ? vector fetch, software clear, or reset a vector fetch generates an interrupt acknowledge signal to clear the cpu interrupt request. software can generate the interrupt acknowledge signal by writing a logic 1 to the ack2 bit in the interrupt status and control register (iscr). the ack2 bit is useful in applications that poll the irq2 pin and require software to clear the irq2 cpu interrupt request. writing to the ack2 bit before leaving an interrupt service routine can also prevent spurious cpu interrupts due to noise. setting ack2 does not affect subsequent transitions on the irq2 pin. a falling edge that occurs after writing to the ack2 bit latches another cpu interrupt request. if the irq2 mask bit, imask2, is clear, the cpu loads the program counter with the vector address at locations $ffe0 and $ffe1. ? return of the irq2 pin to logic 1 as long as the irq2 pin is at logic 0, the irq2 cpu interrupt request remains latched. the vector fetch, software clear, or reset and the return of the irq2 pin to logic 1 can occur in any order. a reset clears the cpu interrupt request and the mode2 bit, clearing the cpu interrupt request even if the pin stays low. if the mode2 bit is clear, the irq2 pin is falling-edge-sensitive only. with mode2 clear, a vector fetch or software clear immediately clears the irq2 cpu interrupt request. the irqf2 bit in the iscr register can be used to check for pending cpu interrupts. the irqf2 bit is not affected by the imask2 bit, which makes it useful in applications where polling is preferred. 6-intirq2_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . irq low-power modes MC68HC708XL36 motorola irq 317 there is no direct way to determine the logic level on the irq2 pin. however, it is possible to use the irqf2 bit in the iscr to infer the state of the irq2 pin. if the mode2 bit is a logic 1, the irqf2 bit in the iscr is the opposite value of the irq2 pin as long as the irq2 cpu interrupt request is cleared. (see figure 1 .) clear the irq2 cpu interrupt request by writing a logic 1 to the acknowledge bit. recall, however, that every falling edge on the irq2 pin latches an irq2 cpu interrupt request. so an additional acknowledge is necessary after each falling edge on irq2 to maintain the opposite relationship between irqf2 and the irq2 pin. set the imask2 bit in the iscr to prevent the irqf2 from generating cpu interrupts when used in this manner. note: to avoid spurious cpu interrupts caused by noise, mask cpu interrupt requests in the interrupt routine when using the level-sensitive interrupt trigger. low-power modes the wait and stop instructions put the mcu in low-power-consump- tion standby modes. wait mode the irq module remains active in wait mode. clearing the imask1 or imask2 bit in the irq status and control register enables irq1 or irq2 cpu interrupt requests to bring the mcu out of wait mode. stop mode the irq module remains active in stop mode. clearing the imask1 or imask2 bit in the irq status and control register enables irq1 or irq2 cpu interrupt requests to bring the mcu out of stop mode. 7-intirq2_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . irq MC68HC708XL36 318 irq motorola irq module during break interrupts the bcfe bit in the break flag control register (bfcr) enables software to clear cpu interrupt requests during the break state. (see break module on page 149.) to allow software to clear irq1 and irq2 cpu interrupt requests during a break interrupt, write a logic 1 to the bcfe bit. if a cpu interrupt request is cleared during the break state, it remains cleared when the mcu exits the break state. to protect cpu interrupt flags during the break state, write a logic 0 to the bcfe bit. with bcfe at logic 0 (its default state), writing to the ack1 and ack2 bits in the irq status and control register during the break state has no effect on the irq interrupt flags. irq status and control register the irq status and control register (iscr) controls and monitors operation of the irq module. the iscr has the following functions: ? shows the state of the irq1 and irq2 interrupt flags ? clears irq1 and irq2 cpu interrupt flags ? masks irq1 and irq2 cpu interrupt requests ? controls triggering sensitivity of the irq1 and irq2 cpu interrupt pins address: $0032 bit 7 654321 bit 0 read: irqf2 0 imask2 mode2 irqf1 0 imask1 mode1 write: ack2 ack1 reset: = unimplemented figure 2. irq status and control register (iscr) 8-intirq2_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . irq irq status and control register MC68HC708XL36 motorola irq 319 irq2f irq2 flag this read-only bit is high when an irq2 cpu interrupt is pending. reset clears irq2f. 1 = irq2 cpu interrupt pending 0 = irq2 cpu interrupt not pending ack2 irq2 interrupt request acknowledge bit writing a logic 1 to this write-only bit clears the irq2 cpu interrupt request. ack2 always reads as logic 0. reset clears ack2. imask2 irq2 interrupt mask bit writing a logic 1 to this read/write bit disables irq2 cpu interrupt requests. reset clears imask2. 1 = irq2 cpu interrupt requests masked 0 = irq2 cpu interrupt requests not masked mode2 irq2 interrupt edge/level select bit this read/write bit controls the triggering sensitivity of the irq2 pin. reset clears mode2. 1 = irq2 cpu interrupt requests on falling edges and low levels 0 = irq2 cpu interrupt requests on falling edges only irq1f irq1 flag this read-only bit is high when an irq1 cpu interrupt is pending. 1 = irq1 cpu interrupt pending 0 = irq1 cpu interrupt not pending ack1 irq1 interrupt request acknowledge bit writing a logic 1 to this write-only bit clears the irq1 cpu interrupt request. ack1 always reads as logic 0. reset clears ack1. imask1 irq1 interrupt mask bit writing a logic 1 to this read/write bit disables irq1 cpu interrupt requests. reset clears imask1. 1 = irq1 cpu interrupt requests masked 0 = irq1 cpu interrupt requests not masked 9-intirq2_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . irq MC68HC708XL36 320 irq motorola mode1 irq1 edge/level select bit this read/write bit controls the triggering sensitivity of the irq1 pin. reset clears mode1. 1 = irq1 cpu interrupt requests on falling edges and low levels 0 = irq1 cpu interrupt requests on falling edges only 10-intirq2_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC708XL36 motorola kbi 321 keyboard interrupt module kbi contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .321 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .323 keyboard initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .325 low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .326 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .326 stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .326 keyboard module during break interrupts . . . . . . . . . . . . . . . . . . . .326 i/o registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .327 keyboard status and control register . . . . . . . . . . . . . . . . . . . . .327 keyboard interrupt enable register . . . . . . . . . . . . . . . . . . . . . . .328 introduction the keyboard module provides eight independently maskable external interrupt pins. features ? eight keyboard interrupt pins with separate keyboard interrupt enable bits and one keyboard interrupt mask ? hysteresis buffers ? programmable edge-only or edge- and level- interrupt sensitivity ? automatic interrupt acknowledge ? exit from low-power modes 1-intkbd8_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . kbi speci?cation MC68HC708XL36 322 kbi motorola figure 1. keyboard module block diagram register name bit 7 654321 bit 0 keyboard status and control register (kbscr) read: 0000 keyf 0 imaskk modek write: ackk reset: 00000000 keyboard interrupt enable register (kbier) read: kbie7 kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset: 00000000 = unimplemented figure 2. i/o register summary table 1. i/o register address summary register kbscr kbier address $001a $001b kb0ie kb7ie . . . keyboard interrup t dq ck clr v dd modek imaskk keyboard interrupt ff request vector fetch decoder ackk internal bus reset to pullup enable kbd7 kbd0 to pullup enable synchronizer keyf 2-intkbd8_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . kbi functional description MC68HC708XL36 motorola kbi 323 functional description writing to the kbie7Ckbie0 bits in the keyboard interrupt enable register independently enables or disables each port d pin as a keyboard interrupt pin. enabling a keyboard interrupt pin also enables its internal pullup device. a logic 0 applied to an enabled keyboard interrupt pin latches a keyboard interrupt request. a keyboard interrupt is latched when one or more keyboard pins goes low after all were high. the modek bit in the keyboard status and control register controls the triggering mode of the keyboard interrupt. ? if the keyboard interrupt is edge-sensitive only, a falling edge on a keyboard pin does not latch an interrupt request if another keyboard pin is already low. to prevent losing an interrupt request on one pin because another pin is still low, software can disable the latter pin while it is low. ? if the keyboard interrupt is falling edge- and low level-sensitive, an interrupt request is present as long as any keyboard pin is low. if the modek bit is set, the keyboard interrupt pins are both falling edge- and low level-sensitive, and both of the following actions must occur to clear a keyboard interrupt request: ? vector fetch or software clear a vector fetch generates an interrupt acknowledge signal to clear the interrupt request. software may generate the interrupt acknowledge signal by writing a logic 1 to the ackk bit in the keyboard status and control register (kbscr). the ackk bit is useful in applications that poll the keyboard interrupt pins and require software to clear the keyboard interrupt request. writing to the ackk bit prior to leaving an interrupt service routine can also prevent spurious interrupts due to noise. setting ackk does not affect subsequent transitions on the keyboard interrupt pins. a falling edge that occurs after writing to the ackk bit latches another interrupt request. if the keyboard interrupt mask bit, imaskk, is clear, the cpu loads the program counter with the vector address at locations $ffde and $ffdf. 3-intkbd8_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . kbi MC68HC708XL36 324 kbi motorola ? return of all enabled keyboard interrupt pins to logic 1 as long as any enabled keyboard interrupt pin is at logic 0, the keyboard interrupt remains set. the vector fetch or software clear and the return of all enabled keyboard interrupt pins to logic 1 may occur in any order. if the modek bit is clear, the keyboard interrupt pin is falling-edge-sensitive only. with modek clear, a vector fetch or software clear immediately clears the keyboard interrupt request. reset clears the keyboard interrupt request and the modek bit, clearing the interrupt request even if a keyboard interrupt pin stays at logic 0. the keyboard flag bit (keyf) in the keyboard status and control register can be used to see if a pending interrupt exists. the keyf bit is not affected by the keyboard interrupt mask bit (imaskk) which makes it useful in applications where polling is preferred. to determine the logic level on a keyboard interrupt pin, use the data direction register to configure the pin as an input and read the data register. note: setting a keyboard interrupt enable bit (kbiex) forces the corresponding keyboard interrupt pin to be an input, overriding the data direction register. however, the data direction register bit must be a logic 0 for software to read the pin. 4-intkbd8_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . kbi keyboard initialization MC68HC708XL36 motorola kbi 325 keyboard initialization when a keyboard interrupt pin is enabled, it takes time for the internal pullup to reach a logic 1. therefore a false interrupt can occur as soon as the pin is enabled. to prevent a false interrupt on keyboard initialization: 1. mask keyboard interrupts by setting the imaskk bit in the keyboard status and control register. 2. enable the kb pins by setting the appropriate kbiex bits in the keyboard interrupt enable register. 3. write to the ackk bit in the keyboard status and control register to clear any false interrupts. 4. clear the imaskk bit. an interrupt signal on an edge-triggered pin can be acknowledged immediately after enabling the pin. an interrupt signal on an edge- and level-triggered interrupt pin must be acknowledged after a delay that depends on the external load. another way to avoid a false interrupt: 1. configure the keyboard pins as outputs by setting the appropriate ddrd bits in data direction register d. 2. write logic 1s to the appropriate port d data register bits. 3. enable the kb pins by setting the appropriate kbiex bits in the keyboard interrupt enable register. 5-intkbd8_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . kbi MC68HC708XL36 326 kbi motorola low-power modes the wait and stop instructions put the mcu in low-power-consump- tion standby modes. wait mode the keyboard module remains active in wait mode. clearing the imaskk bit in the keyboard status and control register enables keyboard interrupt requests to bring the mcu out of wait mode. stop mode the keyboard module remains active in stop mode. clearing the imaskk bit in the keyboard status and control register enables keyboard interrupt requests to bring the mcu out of stop mode. keyboard module during break interrupts the bcfe bit in the break flag control register (bfcr) enables software to clear status bits during the break state. (see break module on page 149.) to allow software to clear the keyf bit during a break interrupt, write a logic 1 to the bcfe bit. if keyf is cleared during the break state, it remains cleared when the mcu exits the break state. to protect the keyf bit during the break state, write a logic 0 to the bcfe bit. with bcfe at logic 0, writing to the keyboard acknowledge bit (ackk) in the keyboard status and control register during the break state has no effect. (see keyboard status and control register on page 327.) 6-intkbd8_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . kbi i/o registers MC68HC708XL36 motorola kbi 327 i/o registers the following registers control and monitor operation of the keyboard module: ? keyboard status and control register (kbscr) ? keyboard interrupt enable register (kbier) keyboard status and control register the keyboard status and control register: ? flags keyboard interrupt requests. ? acknowledges keyboard interrupt requests. ? masks keyboard interrupt requests. ? controls keyboard interrupt triggering sensitivity. bits 7C4 not used these read-only bits always read as logic 0s. keyf keyboard flag bit this read-only bit is set when a keyboard interrupt is pending. reset clears the keyf bit. 1 = keyboard interrupt pending 0 = no keyboard interrupt pending address: $001a bit 7 654321 bit 0 read: 0000 keyf 0 imaskk modek write: ackk reset: 00000000 = unimplemented figure 3. keyboard status and control register (kbscr) 7-intkbd8_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . kbi MC68HC708XL36 328 kbi motorola ackk keyboard acknowledge bit writing a logic 1 to this write-only bit clears the keyboard interrupt request. ackk always reads as logic 0. reset clears ackk. imaskk keyboard interrupt mask bit writing a logic 1 to this read/write bit prevents the output of the keyboard interrupt mask from generating interrupt requests. reset clears the imaskk bit. 1 = keyboard interrupt requests masked 0 = keyboard interrupt requests not masked modek keyboard triggering sensitivity bit this read/write bit controls the triggering sensitivity of the keyboard interrupt pins. reset clears modek. 1 = keyboard interrupt requests on falling edges and low levels 0 = keyboard interrupt requests on falling edges only keyboard interrupt enable register the keyboard interrupt enable register enables or disables each port d pin to operate as a keyboard interrupt pin. kbie[7:0] keyboard interrupt enable bits each of these read/write bits enables the corresponding keyboard interrupt pin to latch interrupt requests. reset clears the keyboard interrupt enable register. 1 = pdx pin enabled as keyboard interrupt pin 0 = pdx pin not enabled as keyboard interrupt pin address: $001b bit 7 654321 bit 0 read: kbie7 kbie6 kbie5 kbie4 kbie3 kbie2 kbie1 kbie0 write: reset: 00000000 figure 4. keyboard interrupt enable register (kbier) 8-intkbd8_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC708XL36 motorola lvi 329 low-voltage inhibit module lvi contents introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .329 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .330 polled lvi operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .330 forced reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .331 lvi status register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .331 lvi interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332 low-power modes. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332 wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332 stop mode. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .332 introduction the low-voltage inhibit module monitors the voltage on the v dd pin and can force a reset when the v dd voltage falls to the lvi trip voltage. features features of the lvi module include the following: ? programmable lvi reset ? programmable power consumption ? programmable stop mode operation 1-lvim2p7_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . lvi MC68HC708XL36 330 lvi motorola functional description figure 1 shows the structure of the lvi module. the lvi module contains a bandgap reference circuit and comparator. clearing the lvi power disable bit, lvipwrd, enables the lvi to monitor v dd voltage. clearing the lvi reset disable bit, lvirstd, enables the lvi module to generate a reset when v dd falls below a voltage, v lvr . setting the lvi enable in stop mode bit, lvistop, enables the lvi to operate in stop mode. lvipwrd, lvirstd, and lvistop are in the configuration register. once an lvi reset occurs, the mcu remains in reset until v dd rises above a voltage, v lvr +h lvr . a power-on reset occurs when v dd reaches v lvr +h lvr .the output of the comparator controls the state of the lviout flag in the lvi status register (lvisr). an lvi reset also drives the rst pin low to provide low-voltage protection to external peripheral devices. figure 1. lvi module block diagram polled lvi operation in applications that can operate at v dd levels below the v lvr level, software can monitor v dd by polling the lviout bit. in the configuration register, the lvipwrd bit must be at logic 0 to enable the lvi module, and the lvirstd bit must be at logic 1 to disable lvi resets. low v dd detector lvipwrd stop instruction lvistop lvi reset lviout v dd > lvi trip = 0 v dd lvi trip = 1 from config from config v dd from config lvirstd 2-lvim2p7_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . lvi lvi status register MC68HC708XL36 motorola lvi 331 forced reset operation in applications that require v dd to remain above the v lvr trip level, enabling lvi resets allows the lvi module to reset the mcu when v dd falls to the v lvr level. in the configuration register, the lvipwrd and lvirstd bits must be at logic 0 to enable the lvi module and to enable lvi resets. lvi status register the lvi status register flags v dd voltages below the v lvr level. lviout lvi output bit this read-only flag becomes set when the v dd voltage falls below the v lvr trip voltage. (see table 1 .) reset clears the lviout bit. address: $fe0f bit 7 654321 bit 0 read: lviout 0000000 write: reset: 00000000 = unimplemented figure 2. lvi status register (lvisr) table 1. lviout bit indication v dd lviout v dd > v lv r + h lv r 0 v dd < v lv r 1 v lv r < v dd < v lv r + h lv r previous value 3-lvim2p7_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . lvi MC68HC708XL36 332 lvi motorola lvi interrupts the lvi module does not generate cpu interrupt requests. low-power modes the stop and wait instructions put the mcu in low power-consump- tion standby modes. wait mode if enabled, the lvi module remains active in wait mode. if enabled to generate resets, the lvi module can generate a reset and bring the mcu out of wait mode. stop mode if enabled, the lvi module remains active in stop mode. if enabled to generate resets, the lvi module can generate a reset and bring the mcu out of stop mode. 4-lvim2p7_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC708XL36 motorola specifications 333 specifications specifications contents preliminary electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . .333 maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .334 functional operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . .335 thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .335 dc electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . .336 control timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .338 spi characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .339 timer interface module characteristics . . . . . . . . . . . . . . . . . . . .343 clock generation module electrical characteristics . . . . . . . . . .343 memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .346 mechanical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .347 preliminary electrical specifications these electrical and timing specifications are design targets and have not been fully characterized. 1-spec_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . speci?cations MC68HC708XL36 334 specifications motorola maximum ratings maximum ratings are the extreme limits to which the mcu can be exposed without permanently damaging it. the mcu contains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in the table below. keep v in and v out within the range v ss (v in or v out ) v dd . connect unused inputs to the appropriate voltage level, either v ss or v dd . 1. voltages referenced to v ss . note: this device is not guaranteed to operate properly at the maximum ratings. refer to table 4 on page 336 and table 5 on page 337 for guaranteed operating conditions. table 1. maximum ratings (1) characteristic symbol value unit supply voltage v dd C0.3 to +6.0 v input voltage v in v ss C 0.3 to v dd + 0.3 v programming voltage v pp v ss C 0.3 to + 14.0 v maximum current per pin excluding v dd and v ss i 25 ma storage temperature t stg C55 to +150 c maximum current out of v ss i mvss 100 ma maximum current into v dd i mvdd 100 ma 2-spec_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications preliminary electrical specifications MC68HC708XL36 motorola specifications 335 functional operating range thermal characteristics 1. power dissipation is a function of temperature. 2. k is a constant unique to the device. k can be determined for a known t a and measured p d . with this value of k, p d and t j can be determined for any value of t a . table 2. operating range characteristic symbol value unit operating temperature range t a C40 to +85 c operating voltage range v dd 3.3 10% 5.0 10% v table 3. thermal characteristics characteristic symbol value unit thermal resistance qfp (64 pin) sdip (56 pin) q ja 85 50 c/w i/o pin power dissipation p i/o user-determined w power dissipation (1) p d p d = (i dd v dd ) + p i/o = k/(t j + 273 c) w constant (2) k p j x (t a + 273 c ) + p d 2 q ja w c average junction temperature t j t a + (p d q ja ) c maximum junction temperature t jm 125 c 3-spec_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . speci?cations MC68HC708XL36 336 specifications motorola dc electrical characteristics 1. v dd = 5.0 vdc 10%, v ss = 0 vdc, t a = t l to t h , unless otherwise noted. 2. typical values reflect average measurements at midpoint of voltage range, 25 c only. 3. run (operating) i dd measured using external square wave clock source (f osc = 32.8 mhz). all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. c l = 20 pf on osc2. all ports configured as inputs. osc2 capacitance linearly affects run i dd . measured with all modules enabled. 4. wait i dd measured using external square wave clock source (f osc = 32.8 mhz). all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. c l = 20 pf on osc2. all ports configured as inputs. osc2 ca- pacitance linearly affects wait i dd . measured with pll and lvi enabled. 5. stop i dd measured with osc1 = v ss . 6. maximum is highest voltage that por is guaranteed. 7. maximum is highest voltage that por is possible. 8. if minimum v dd is not reached before the internal por reset is released, rst must be driven low externally until minimum v dd is reached. table 4. dc electrical characteristics (v dd = 5.0 vdc 10%) (1) characteristic symbol min typ (2) max unit output high voltage (i load = C2.0 ma) all i/o pins v oh v dd C 0.8 v output low voltage (i load = 1.6 ma) all i/o pins v ol 0.4 v input high voltage all ports, irqs, reset, osc1 v ih 0.7 x v dd v dd v input low voltage all ports, irqs, reset, osc1 v il v ss 0.3 x v dd v v dd supply current run (3) wait (4) stop (5) 25 c 0 c to 85 c 25 c with lvi enabled 0 c to 85 c with lvi enabled i dd 30 12 5 15 320 380 ma ma m a m a m a m a i/o ports hi-z leakage current i il 10 m a input current i in 1 m a capacitance ports (input or output) c out c in 12 8 pf low-voltage inhibit reset v lv r 2.6 2.7 2.8 v low-voltage inhibit reset/recover hysteresis h lv r 60 80 100 mv por rearm voltage (6) v por 0 100 mv por reset voltage (7) v porrst 0 700 800 mv por rise time ramp rate (8) r por 0.035 v/ms 4-spec_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications preliminary electrical specifications MC68HC708XL36 motorola specifications 337 1. v dd = 3.3 vdc 10%, v ss = 0 vdc, t a = t l to t h , unless otherwise noted. 2. typical values reflect average measurements at midpoint of voltage range, 25 c only. 3. run (operating) i dd measured using external square wave clock source (f osc = 16.4 mhz). all inputs 0.2 v from rail. no dc loads. less than 100 pf on all outputs. c l = 20 pf on osc2. all ports configured as inputs. osc2 capacitance linearly affects run i dd . measured with all modules enabled. 4. wait i dd measured using external square wave clock source (f osc = 16.4 mhz). all inputs 0.2v from rail. no dc loads. less than 100 pf on all outputs. c l = 20 pf on osc2. all ports configured as inputs. osc2 capac- itance linearly affects wait i dd . measured with pll and lvi enabled. 5. stop i dd measured with osc1 = v ss . 6. maximum is highest voltage that por is guaranteed. 7. maximum is highest voltage that por is possible. 8. if minimum v dd is not reached before the internal por reset is released, rst must be driven low externally until minimum v dd is reached. table 5. dc electrical characteristics (v dd = 3.3 vdc 10%) (1) characteristic symbol min typ (2) max unit output high voltage (i load = C2.0 ma) all ports v oh v dd C 0.8 v output low voltage (i load = 1.6 ma) all ports v ol 0.4 v input high voltage all ports, irqs, reset, osc1 v ih 0.7 x v dd v dd v input low voltage all ports, irqs, reset, osc1 v il v ss 0.3 x v dd v v dd supply current run (3) wait (4) stop (5) 25 c 0 c to 85 c 25 c with lvi enabled 0 c to 85 c with lvi enabled i dd 10 6 3 10 200 250 ma ma m a m a m a m a i/o ports hi-z leakage current i il 10 m a input current i in 1 m a capacitance ports (input or output) c out c in 12 8 pf low-voltage inhibit reset v lv r 2.6 2.7 2.8 v low-voltage inhibit reset/recover hysteresis h lv r 60 80 100 mv por rearm voltage (6) v por 0 200 mv por reset voltage (7) v porrst 0 700 800 mv por rise time ramp rate (8) r por 0.02 v/ms 5-spec_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . speci?cations MC68HC708XL36 338 specifications motorola control timing 1. v ss = 0 vdc; timing shown with respect to 20% v dd and 70% v ss unless noted 2. see table 11 and table 12 for more information. 3. no more than 10% duty cycle deviation from 50% 4. some modules may require a minimum frequency greater than dc for proper operation. see appropriate table for this information. 5. minimum pulse width reset is guaranteed to be recognized. it is possible for a smaller pulse width to cause a reset. 6. minimum pulse width is for guaranteed interrupt. it is possible for a smaller pulse width to be recognized. 1. v ss = 0 vdc; timing shown with respect to 20% v dd and 70% v ss unless noted 2. see table 11 and table 12 for more information. 3. no more than 10% duty cycle deviation from 50% 4. some modules may require a minimum frequency greater than dc for proper operation. see appropriate table for this information. 5. minimum pulse width reset is guaranteed to be recognized. it is possible for a smaller pulse width to cause a reset. 6. minimum pulse width is for guaranteed interrupt. it is possible for a smaller pulse width to be recognized. table 6. control timing (v dd = 5.0 vdc 10%) (1) characteristic symbol min max unit frequency of operation (2) crystal option external clock option (3) f osc 1 dc (4) 8 32.8 mhz internal operating frequency f op 8.2 mhz reset input pulse width low (5) t irl 50 ns irq interrupt pulse width low (6) (edge-triggered) t ilih 50 ns table 7. control timing (v dd = 3.3 vdc 10%) (1) characteristic symbol min max unit frequency of operation (2) crystal option external clock option (3) f osc 1 dc (4) 8 16.4 mhz internal operating frequency f op 4.1 mhz reset input pulse width low (5) t irl 125 ns irq interrupt pulse width low (6) (edge-triggered) t ilih 125 ns 6-spec_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications preliminary electrical specifications MC68HC708XL36 motorola specifications 339 spi characteristics 1. all timing is shown with respect to 20% v dd and 70% v dd , unless noted; 100 pf load on all spi pins. 2. numbers refer to dimensions in figure 1 and figure 2 . 3. time to data active from high-impedance state 4. hold time to high-impedance state 5. with 100 pf on all spi pins table 8. spi timing (v dd = 5.0 vdc 10%) (1) diagram number (2) characteristic symbol min max unit operating frequency master slave f op(m) f op(s) f op /128 dc f op /2 f op mhz 1 cycle time master slave t cyc(m) t cyc(s) 2 1 128 t cyc 2 enable lead time t lead(s) 15 ns 3 enable lag time t lag(s) 15 ns 4 clock (sck) high time master slave t sckh(m) t sckh(s) 100 50 ns 5 clock (sck) low time master slave t sckl(m) t sckl(s) 100 50 ns 6 data setup time (inputs) master slave t su(m) t su(s) 45 5 ns 7 data hold time (inputs) master slave t h(m) t h(s) 0 15 ns 8 access time, slave (3) cpha = 0 cpha = 1 t a(cp0) t a(cp1) 0 0 40 20 ns 9 disable time, slave (4) t dis(s) 25ns 10 data valid time (after enable edge) master slave (5) t v(m) t v(s) 10 40 ns 11 data hold time (outputs, after enable edge) master slave t ho(m) t ho(s) 0 5 ns 7-spec_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . speci?cations MC68HC708XL36 340 specifications motorola 1. all timing is shown with respect to 20% v dd and 70% v dd , unless noted; 100 pf load on all spi pins. 2. numbers refer to dimensions in figure 1 and figure 2 . 3. time to data active from high-impedance state 4. hold time to high-impedance state 5. with 100 pf on all spi pins table 9. spi timing (v dd = 3.3 vdc 10%) (1) diagram number (2) characteristic symbol min max unit operating frequency master slave f op(m) f op(s) f op /128 dc f op /2 f op mhz 1 cycle time master slave t cyc(m) t cyc(s) 2 1 128 t cyc 2 enable lead time t lead(s) 30 ns 3 enable lag time t lag(s) 30 ns 4 clock (sck) high time master slave t sckh(m) t sckh(s) 200 100 ns 5 clock (sck) low time master slave t sckl(m) t sckl(s) 200 100 ns 6 data setup time (inputs) master slave t su(m) t su(s) 90 10 ns 7 data hold time (inputs) master slave t h(m) t h(s) 0 30 ns 8 access time, slave (3) cpha = 0 cpha = 1 t a(cp0) t a(cp1) 0 0 80 40 ns 9 disable time, slave (4) t dis(s) 50ns 10 data valid time (after enable edge) master slave (5) t v(m) t v(s) 20 80 ns 11 data hold time (outputs, after enable edge) master slave t ho(m) t ho(s) 0 10 ns 8-spec_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications preliminary electrical specifications MC68HC708XL36 motorola specifications 341 figure 1. spi master timing note note: this first clock edge is generated internally, but is not seen at the sck pin. ss pin of master held high msb in ss input sck (cpol = 0) output sck cpol = 1 output miso input mosi output note 4 5 5 1 4 bits 6C1 lsb in master msb out bits 6C1 master lsb out 10 11 10 11 7 6 note note: this last clock edge is generated internally, but is not seen at the sck pin. ss pin of master held high msb in ss input sck (cpol = 0) output sck (cpol = 1) output miso input mosi output note 4 5 5 1 4 bits 6C1 lsb in master msb out bits 6C1 master lsb out 10 11 10 11 7 6 a) spi master timing (cpha = 0) b) spi master timing (cpha = 1) 9-spec_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . speci?cations MC68HC708XL36 342 specifications motorola figure 2. spi slave timing note: not defined but normally msb of character just received slave ss input sck (cpol = 0) input sck (cpol = 1) input miso input mosi output 4 5 5 1 4 msb in bits 6C1 8 6 10 11 11 note slave lsb out 9 3 lsb in 2 7 bits 6C1 msb out note: not defined but normally lsb of character previously transmitted slave ss input sck (cpol = 0) input sck (cpol = 1) input miso output mosi input 4 5 5 1 4 msb in bits 6C1 8 6 10 note slave lsb out 9 3 lsb in 2 7 bits 6C1 msb out 10 a) spi slave timing (cpha = 0) b) spi slave timing (cpha = 1) 11 11 10-spec_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications preliminary electrical specifications MC68HC708XL36 motorola specifications 343 timer interface module characteristics clock generation module electrical characteristics 1. fundamental mode crystals only 2. consult crystal manufacturers data. 3. not required 4. c byp must provide low ac impedance from f = f xclk /100 to 100 f vclk , so series resistance must be considered. table 10. tim timing characteristic symbol min max unit input capture pulse width t tih , t til 125 ns input clock pulse width t tch , t tcl (1/f op ) + 5 ns table 11. cgm component speci?cations characteristic symbol min typ max unit crystal (x1) frequency (mhz) (1) f xclk 1 4.9152 8 mhz crystal load capacitance (2) c l pf crystal fixed capacitance (2) c 1 2 c l pf crystal tuning capacitance (2) c 2 2 c l pf feedback bias resistor r b 1 m w series resistor (3) r s 0 3.3 k w filter capacitor c f c fact (v dda /f xclk ) pf bypass capacitor (4) c byp 0.1 m f 11-spec_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . speci?cations MC68HC708XL36 344 specifications motorola 1. 5.0 v 10% v dd only 2. 3.3 v 10% v dd only table 12. cgm operating conditions characteristic symbol min typ max unit crystal reference frequency f xclk 1 8 mhz range nominal multiplier f nom 4.9152 mhz vco center-of-range frequency (1) f vrs 4.9152 32.8 mhz medium voltage vco center-of-range frequency (2) 4.9152 16.4 mhz vco frequency multiplier n 1 15 vco center-of-range multiplier l 1 15 vco operating frequency f vclk f vrsmin f vrsmax mhz 12-spec_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications preliminary electrical specifications MC68HC708XL36 motorola specifications 345 1. if c f chosen correctly 2. deviation of average bus frequency over 2 ms. n = vco frequency multiplier . table 13. cgm acquisition and lock time speci?cations description symbol min typ max unit filter capacitor multiply factor c fact 0.0154 f/sv acquisition mode time factor k acq 0.1135 v tracking mode time factor k trk 0.0174 v manual mode time to stable (1) t acq s manual stable to lock time (1) t al s manual acquisition time t lock t acq + t al s tracking mode entry frequency tolerance d trk 0 3.6% acquisition mode entry frequency tolerance d acq 6.3% 7.2% lock entry frequency tolerance d lock 0 0.9% lock exit frequency tolerance d unl 0.9% 1.8% reference cycles per acquisition mode measurement n acq 32 cyc. reference cycles per tracking mode measurement n trk 128 cyc. automatic mode time to stable (1) t acq s automatic stable to lock time (1) t al s automatic lock time t lock t acq +t al s pll jitter (2) f j 0 f crys 0.025% 2 p n/4 hz 8v dda f xclk k acq ------------------------------ 4 v dda f xclk k trk --------------------------- n acq f xclk ----------- - 8v dda f xclk k acq ------------------------------ n trk f xclk ---------- - 4 v dda f xclk k trk --------------------------- 13-spec_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . speci?cations MC68HC708XL36 346 specifications motorola memory characteristics table 14. memory characteristics characteristic symbol min typ max unit eprom programming voltage v pp 12.5 13.0 13.5 v eprom data retention t dret 10.0 years eprom programming time t epgm 1 ms/byte ram data retention voltage v rm 0.7 v 14-spec_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications mechanical specifications MC68HC708XL36 motorola specifications 347 mechanical specifications figure 3. case outline drawing 859-01 a b t 56 29 128 seating plane j 56 pl d 56 pl s a m 0.25 (0.010) t n f g e s b m 0.25 (0.010) t k c h l m dim min max min max millimeters inches a 2.035 2.065 51.69 52.45 b 0.540 0.560 13.72 14.22 c 0.155 0.200 3.94 5.08 d 0.014 0.022 0.36 0.56 e 0.035 bsc 0.89 bsc f 0.032 0.046 0.81 1.17 g 0.070 bsc 1.778 bsc h 0.300 bsc 7.62 bsc j 0.008 0.015 0.20 0.38 k 0.115 0.135 2.92 3.43 l 0.600 bsc 15.24 bsc m 0 15 0 15 n 0.020 0.040 0.51 1.02 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: inch. 3. dimension l to center of lead when formed parallel. 4. dimensions a and b do not include mold flash. maximum mold flash 0.25 (0.010) 15-spec_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . speci?cations MC68HC708XL36 348 specifications motorola figure 4. case outline drawing 840b-01 l l a b detail a d b a s v detail a p b b d a, b, d c c e h g m m detailc seating plane datum plane 1 16 h 0.01 (0.004) r detail c datum plane h t u q k w x s ab m 0.20 (0.008) d s h s ab m 0.20 (0.008) d s c 0.05 (0.002) ab s ab m 0.20 (0.008) d s c 0.05 (0.002) ab s ab m 0.20 (0.008) d s h 48 33 s ab m 0.02 (0.008) d s c n f j base metal 32 49 17 64 dim min max min max inches millimeters a 13.90 14.10 0.547 0.555 b 13.90 14.10 0.547 0.555 c 2.15 2.45 0.085 0.096 d 0.30 0.45 0.012 0.018 e 2.00 2.40 0.079 0.094 f 0.30 0.40 0.012 0.016 g 0.80 bsc 0.031 bsc h 0.25 0.010 j 0.13 0.23 0.005 0.009 k 0.65 0.95 0.026 0.037 l 12.00 ref 0.472 ref m 5 10 5 10 n 0.13 0.17 0.005 0.007 p 0.40 bsc 0.016 bsc q 0 7 0 7 r 0.13 0.30 0.005 0.012 s 16.95 17.45 0.667 0.687 t 0.13 0.005 u 0 0 v 16.95 17.45 0.667 0.687 w 0.35 0.45 0.014 0.018 x 1.6 ref 0.063 ref notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane h is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums a, b and d to be determined at datum plane h. 5. dimensions s and v to be determined at seating plane c. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane h. 7. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.08 (0.003) per side. total in excess of the d dimension at maximum material condition. dambar cannot be located on the lower radius or the foot. 16-spec_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . specifications mechanical specifications MC68HC708XL36 motorola specifications 349 figure 5. case outline drawing 840c-04 ???? ??? ? ???? g h e c detail a l a 48 s l d a b 0.05 (0.002) ab s ab m 0.20 (0.008) d s h s ab m 0.20 (0.008) d s c b v 0.05 (0.002) d s ab m 0.20 (0.008) d s h s ab m 0.20 (0.008) d s c seating plane datum plane c h 49 33 32 64 17 1 16 detail c 0.10 (0.004) s ab m 0.20 (0.008) d s c section bb f n d base j metal detail a p bb a, b, d notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane h is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums ab and d to be determined at datum plane h. 5. dimensions s and v to be determined at seating plane c. 6. dimensions a and b do not include mold protrusion. allowable protrusion is 0.25 (0.010) per side. dimensions a and b do include mold mismatch and are determined at datum plane h. 7. dimension d does not include dambar protrusion. dambar protrusion shall not cause the d dimension to exceed 0.53 (0.021). dambar cannot be located on the lower radius or the foot. 8. dimension k is to be measured from the theoretical intersection of lead foot and leg centerlines. dim min max min max inches millimeters a 13.90 14.10 0.547 0.555 b 13.90 14.10 0.547 0.555 c 2.07 2.46 0.081 0.097 d 0.30 0.45 0.012 0.018 e 2.00 0.079 f 0.30 0.012 g 0.80 bsc 0.031 bsc h 0.067 0.250 0.003 0.010 j 0.130 0.230 0.005 0.090 k 0.50 0.66 0.020 0.026 l 12.00 ref 0.472 ref m 5 10 5 10 n 0.130 0.170 0.005 0.007 p 0.40 bsc 0.016 bsc q 2 8 2 8 r 0.13 0.30 0.005 0.012 s 16.20 16.60 0.638 0.654 t 0.20 ref 0.008 ref u 0 0 v 16.20 16.60 0.638 0.654 x 1.10 1.30 0.043 0.051 2.40 0.094 detail c seating plane m u t r q k x m 17-spec_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . speci?cations MC68HC708XL36 350 specifications motorola figure 6. case outline drawing 963-02 notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. datum plane h is located at bottom of lead and is coincident with the lead where the lead exits the plastic body at the bottom of the parting line. 4. datums a, b and d to be determined at datum plane h. 5. dimensions s and v to be determined at seating plane c. 6. dimensions a and b define maximum ceramic body dimension including glass protrusion and mismatch between ceramic body and cover. dim a min max min max inches 13.90 14.10 0.547 0.555 millimeters b 13.90 14.10 0.547 0.555 c 3.00 4.11 0.118 0.162 d 0.30 0.45 0.012 0.018 e 2.54 3.22 0.100 0.127 f 0.30 0.40 0.012 0.016 g 0.80 bsc 0.031 bsc h 0.45 0.89 0.018 0.035 j 0.13 0.23 0.005 0.009 k 0.65 0.95 0.026 0.037 l 12.00 ref 0.472 ref n 0.13 0.17 0.005 0.007 p 0.40 bsc 0.016 bsc q 0 7 0 7 r 0.13 0.30 0.005 0.012 s 16.95 17.45 0.667 0.687 t 0.13 0.005 u 0 0 v 16.95 17.45 0.667 0.687 w 0.35 0.45 0.014 0.018 x 1.60 ref 0.063 ref l l b v a s g h e c seating plane 0.01 (0.004) detail c detail a q u x t r w k datum plane detail c 1 16 17 32 33 48 49 64 a b h datum plane c d h b b p detail a d f j n view rotated 90 clockwise section bb base metal a, b, d s ab m 0.02 (0.008) d s c s ab m 0.20 (0.008) d s c ab 0.05 (0.002) s ab m 0.20 (0.008) d s h s ab m 0.20 (0.008) d s c ab 0.05 (0.002) s ab m 0.20 (0.008) d s h 18-spec_a f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC708XL36 motorola glossary 351 glossary glossary a see accumulator (a). accumulator (a) an 8-bit general-purpose register in the cpu08. the cpu08 uses the accumulator to hold operands and results of arithmetic and logic operations. acquisition mode a mode of pll operation during startup before the pll locks on a frequency. also see "tracking mode." address bus the set of wires that the cpu or dma uses to read and write memory locations. addressing mode the way that the cpu determines the operand address for an instruction. the m68hc08 cpu has 16 addressing modes. alu see arithmetic logic unit (alu). arithmetic logic unit (alu) the portion of the cpu that contains the logic circuitry to perform arithmetic, logic, and manipulation operations on operands. asynchronous refers to logic circuits and operations that are not synchronized by a common reference signal. baud rate the total number of bits transmitted per unit of time. bcd see binary-coded decimal (bcd). binary relating to the base 2 number system. binary number system the base 2 number system, having two digits, 0 and 1. binary arithmetic is convenient in digital circuit design because digital circuits have two permissible voltage levels, low and high. the binary digits 0 and 1 can be interpreted to correspond to the two digital voltage levels. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . glossary MC68HC708XL36 352 glossary motorola binary-coded decimal (bcd) a notation that uses 4-bit binary numbers to represent the 10 decimal digits and that retains the same positional structure of a decimal number. for example, 234 (decimal) = 0010 0011 0100 (bcd) bit a binary digit. a bit has a value of either logic 0 or logic 1. branch instruction an instruction that causes the cpu to continue processing at a memory location other than the next sequential address. break module a module in the m68hc08 family. the break module allows software to halt program execution at a programmable point in order to enter a background routine. breakpoint a number written into the break address registers of the break module. when a number appears on the internal address bus that is the same as the number in the break address registers, the cpu executes the software interrupt instruction (swi). break interrupt a software interrupt caused by the appearance on the internal address bus of the same value that is written in the break address registers. bus a set of wires that transfers logic signals. bus clock the bus clock is derived from the cgmout output from the cgm. the bus clock frequency, f op , is equal to the frequency of the oscillator output, cgmxclk, divided by four. byte a set of eight bits. c the carry/borrow bit in the condition code register. the cpu08 sets the carry/borrow bit when an addition operation produces a carry out of bit 7 of the accumulator or when a subtraction operation requires a borrow. some logical operations and data manipulation instructions also clear or set the carry/borrow bit (as in bit test and branch instructions and shifts and rotates). ccr see condition code register. central processor unit (cpu) the primary functioning unit of any computer system. the cpu controls the execution of instructions. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . glossary MC68HC708XL36 motorola glossary 353 cgm see clock generator module (cgm). clear to change a bit from logic 1 to logic 0; the opposite of set. clock a square wave signal used to synchronize events in a computer. clock generator module (cgm) a module in the m68hc08 family. the cgm generates a base clock signal from which the system clocks are derived. the cgm may include a crystal oscillator circuit and or phase-locked loop (pll) circuit. comparator a device that compares the magnitude of two inputs. a digital comparator defines the equality or relative differences between two binary numbers. computer operating properly module (cop) a counter module in the m68hc08 family that resets the mcu if allowed to overflow. condition code register (ccr) an 8-bit register in the cpu08 that contains the interrupt mask bit and five bits that indicate the results of the instruction just executed. control bit one bit of a register manipulated by software to control the operation of the module. control unit one of two major units of the cpu. the control unit contains logic functions that synchronize the machine and direct various operations. the control unit decodes instructions and generates the internal control signals that perform the requested operations. the outputs of the control unit drive the execution unit, which contains the arithmetic logic unit (alu), cpu registers, and bus interface. cop see "computer operating properly module (cop)." counter clock the input clock to the tim counter. this clock is an output of the prescaler sub-module. the frequency of the counter clock is f tcnt , and the period is t tcnt . cpu see central processor unit (cpu). cpu08 the central processor unit of the m68hc08 family. cpu clock the cpu clock is derived from the cgmout output from the cgm. the cpu clock frequency is equal to the frequency of the oscillator output, cgmxclk, divided by four. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . glossary MC68HC708XL36 354 glossary motorola cpu cycles a cpu clock cycle is one period of the internal bus-rate clock, f op , normally derived by dividing a crystal oscillator source by two or more so the high and low times will be equal. the length of time required to execute an instruction is measured in cpu clock cycles. cpu registers memory locations that are wired directly into the cpu logic instead of being part of the addressable memory map. the cpu always has direct access to the information in these registers. the cpu registers in an m68hc08 are: ? a (8-bit accumulator) ? h:x (16-bit index register) ? sp (16-bit stack pointer) ? pc (16-bit program counter) ? ccr (condition code register containing the v, h, i, n, z, and c bits) csic customer-specified integrated circuit cycle time the period of the operating frequency: t cyc = 1/f op . decimal number system base 10 numbering system that uses the digits zero through nine. direct memory access module (dma) a m68hc08 family module that can perform data transfers between any two cpu-addressable locations without cpu intervention. for transmitting or receiving blocks of data to or from peripherals, dma transfers are faster and more code-efficient than cpu interrupts. dma see "direct memory access module (dma)." dma service request a signal from a peripheral to the dma module that enables the dma module to transfer data. duty cycle a ratio of the amount of time the signal is on versus the time it is off. duty cycle is usually represented by a percentage. eeprom electrically erasable, programmable, read-only memory. a nonvolatile type of memory that can be electrically reprogrammed. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . glossary MC68HC708XL36 motorola glossary 355 eprom erasable, programmable, read-only memory. a non-volatile type of memory that can be erased by exposure to an ultraviolet light source and then reprogrammed. exception an event such as an interrupt or a reset that stops the sequential execution of the instructions in the main program. external interrupt module (irq) a module in the m68hc08 family with both dedicated external interrupt pins and port pins that can be enabled as interrupt pins. fetch to copy data from a memory location into the accumulator. firmware instructions and data programmed into nonvolatile memory. free-running counter a device that counts from zero to a predetermined number, then rolls over to zero and begins counting again. full-duplex transmission communication on a channel in which data can be sent and received simultaneously. h the upper byte of the 16-bit index register (h:x) in the cpu08. h the half-carry bit in the condition code register of the cpu08. this bit indicates a carry from the low-order four bits of the accumulator value to the high-order four bits. the half-carry bit is required for binary-coded decimal arithmetic operations. the decimal adjust accumulator (daa) instruction uses the state of the h and c bits to determine the appropriate correction factor. hexadecimal base 16 numbering system that uses the digits 0 through 9 and the letters a through f. high byte the most significant eight bits of a word. illegal address an address not within the memory map illegal opcode a nonexistent opcode. i the interrupt mask bit in the condition code register of the cpu08. when i is set, all interrupts are disabled. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . glossary MC68HC708XL36 356 glossary motorola index register (h:x) a 16-bit register in the cpu08. the upper byte of h:x is called h. the lower byte is called x. in the indexed addressing modes, the cpu uses the contents of h:x to determine the effective address of the operand. h:x can also serve as a temporary data storage location. input/output (i/o) input/output interfaces between a computer system and the external world. a cpu reads an input to sense the level of an external signal and writes to an output to change the level on an external signal. instructions operations that a cpu can perform. instructions are expressed by programmers as assembly language mnemonics. a cpu interprets an opcode and its associated operand(s) and instruction. interrupt a temporary break in the sequential execution of a program to respond to signals from peripheral devices by executing a subroutine. interrupt request a signal from a peripheral to the cpu intended to cause the cpu to execute a subroutine. i/o see input/output (i/0). irq see "external interrupt module (irq)." jitter short-term signal instability. latch a circuit that retains the voltage level (logic 1 or logic 0) written to it for as long as power is applied to the circuit. latency the time lag between instruction completion and data movement. least significant bit (lsb) the rightmost digit of a binary number. logic 1 a voltage level approximately equal to the input power voltage (v dd ). logic 0 a voltage level approximately equal to the ground voltage (v ss ). low byte the least significant eight bits of a word. low voltage inhibit module (lvi) a module in the m68hc08 family that monitors power supply voltage. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . glossary MC68HC708XL36 motorola glossary 357 lvi see "low voltage inhibit module (lvi)." m68hc08 a motorola family of 8-bit mcus. mark/space the logic 1/logic 0 convention used in formatting data in serial communication. mask 1. a logic circuit that forces a bit or group of bits to a desired state. 2. a photomask used in integrated circuit fabrication to transfer an image onto silicon. mask option an optional microcontroller feature that the customer chooses to enable or disable. mask option register (mor) an eprom location containing bits that enable or disable certain mcu features. mcu microcontroller unit. see microcontroller. memory location each m68hc08 memory location holds one byte of data and has a unique address. to store information in a memory location, the cpu places the address of the location on the address bus, the data information on the data bus, and asserts the write signal. to read information from a memory location, the cpu places the address of the location on the address bus and asserts the read signal. in response to the read signal, the selected memory location places its data onto the data bus. memory map a pictorial representation of all memory locations in a computer system. microcontroller microcontroller unit (mcu). a complete computer system, including a cpu, memory, a clock oscillator, and input/output (i/o) on a single integrated circuit. modulo counter a counter that can be programmed to count to any number from zero to its maximum possible modulus. monitor rom a section of rom that can execute commands from a host computer for testing purposes. mor see "mask option register (mor)." most significant bit (msb) the leftmost digit of a binary number. multiplexer a device that can select one of a number of inputs and pass the logic level of that input on to the output. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . glossary MC68HC708XL36 358 glossary motorola n the negative bit in the condition code register of the cpu08. the cpu sets the negative bit when an arithmetic operation, logical operation, or data manipulation produces a negative result. nibble a set of four bits (half of a byte). object code the output from an assembler or compiler that is itself executable machine code, or is suitable for processing to produce executable machine code. opcode a binary code that instructs the cpu to perform an operation. open-drain an output that has no pullup transistor. an external pullup device can be connected to the power supply to provide the logic 1 output voltage. operand data on which an operation is performed. usually a statement consists of an operator and an operand. for example, the operator may be an add instruction, and the operand may be the quantity to be added. oscillator a circuit that produces a constant frequency square wave that is used by the computer as a timing and sequencing reference. otprom one-time programmable read-only memory. a nonvolatile type of memory that cannot be reprogrammed. overflow a quantity that is too large to be contained in one byte or one word. page zero the first 256 bytes of memory (addresses $0000C$00ff). parity an error-checking scheme that counts the number of logic 1s in each byte transmitted. in a system that uses odd parity, every byte is expected to have an odd number of logic ones. in an even parity system, every byte should have an even number of logic ones. in the transmitter, a parity generator appends an extra bit to each byte to make the number of logic 1s odd for odd parity or even for even parity. a parity checker in the receiver counts the number of logic 1s in each byte. the parity checker generates an error signal if it finds a byte with an incorrect number of logic 1s. pc see program counter (pc). peripheral a circuit not under direct cpu control. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . glossary MC68HC708XL36 motorola glossary 359 phase-locked loop (pll) a oscillator circuit in which the frequency of the oscillator is synchronized to a reference signal. pll see "phase-locked loop (pll)." pointer pointer register. an index register is sometimes called a pointer register because its contents are used in the calculation of the address of an operand, and therefore points to the operand. polarity the two opposite logic levels, logic 1 and logic 0, which correspond to two different voltage levels, v dd and v ss . polling periodically reading a status bit to monitor the condition of a peripheral device. port a set of wires for communicating with off-chip devices. prescaler a circuit that generates an output signal related to the input signal by a fractional scale factor such as 1/2, 1/8, 1/10 etc. program a set of computer instructions that cause a computer to perform a desired operation or operations. program counter (pc) a 16-bit register in the cpu08. the pc register holds the address of the next instruction or operand that the cpu will use. pull an instruction that copies into the accumulator the contents of a stack ram location. the stack ram address is in the stack pointer. pullup a transistor in the output of a logic gate that connects the output to the logic 1 voltage of the power supply. pulse-width the amount of time a signal is on as opposed to being in its off state. pulse-width modulation (pwm) controlled variation (modulation) of the pulse width of a signal with a constant frequency. push an instruction that copies the contents of the accumulator to the stack ram. the stack ram address is in the stack pointer. pwm period the time required for one complete cycle of a pwm waveform. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . glossary MC68HC708XL36 360 glossary motorola ram random access memory. all ram locations can be read or written by the cpu. the contents of a ram memory location remain valid until the cpu writes a different value or until power is turned off. rc circuit a circuit consisting of capacitors and resistors having a defined time constant. read to copy the contents of a memory location to the accumulator. register a circuit that stores a group of bits. reserved memory location a memory location that is used only in special factory-test modes. writing to a reserved location has no effect. reading a reserved location returns an unpredictable value. reset to force a device to a known condition. rom read-only memory. a type of memory that can be read but cannot be changed (written). the contents of rom must be specified before manufacturing the mcu. sci see "serial communication interface module (sci)." serial pertaining to sequential transmission over a single line. serial communications interface module (sci) a module in the m68hc08 family that supports asynchronous communication. serial peripheral interface module (spi) a module in the m68hc08 family that supports synchronous communication. set to change a bit from logic 0 to logic 1; opposite of clear. shift register a chain of circuits that can retain the logic levels (logic 1 or logic 0) written to them and that can shift the logic levels to the right or left through adjacent circuits in the chain. signed a binary number notation that accommodates both positive and negative numbers. the most significant bit is used to indicate whether the number is positive or negative, normally logic 0 for positive and logic 1 for negative. the other seven bits indicate the magnitude of the number. software instructions and data that control the operation of a microcontroller. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . glossary MC68HC708XL36 motorola glossary 361 software interrupt (swi) an instruction that causes an interrupt and its associated vector fetch. spi see "serial peripheral interface module (spi)." stack a portion of ram reserved for storage of cpu register contents and subroutine return addresses. stack pointer (sp) a 16-bit register in the cpu08 containing the address of the next available storage location on the stack. start bit a bit that signals the beginning of an asynchronous serial transmission. status bit a register bit that indicates the condition of a device. stop bit a bit that signals the end of an asynchronous serial transmission. subroutine a sequence of instructions to be used more than once in the course of a program. the last instruction in a subroutine is a return from subroutine (rts) instruction. at each place in the main program where the subroutine instructions are needed, a jump or branch to subroutine (jsr or bsr) instruction is used to call the subroutine. the cpu leaves the flow of the main program to execute the instructions in the subroutine. when the rts instruction is executed, the cpu returns to the main program where it left off. synchronous refers to logic circuits and operations that are synchronized by a common reference signal. tim see "timer interface module (tim)." timer interface module (tim) a module used to relate events in a system to a point in time. timer a module used to relate events in a system to a point in time. toggle to change the state of an output from a logic 0 to a logic 1 or from a logic 1 to a logic 0. tracking mode mode of low-jitter pll operation during which the pll is locked on a frequency. also see "acquisition mode." f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . glossary MC68HC708XL36 362 glossary motorola twos complement a means of performing binary subtraction using addition techniques. the most significant bit of a twos complement number indicates the sign of the number (1 indicates negative). the twos complement negative of a number is obtained by inverting each bit in the number and then adding 1 to the result. unbuffered utilizes only one register for data; new data overwrites current data. unimplemented memory location a memory location that is not used. writing to an unimplemented location has no effect. reading an unimplemented location returns an unpredictable value. executing an opcode at an unimplemented location causes an illegal address reset. v the overflow bit in the condition code register of the cpu08. the cpu08 sets the v bit when a two's complement overflow occurs. the signed branch instructions bgt, bge, ble, and blt use the overflow bit. variable a value that changes during the course of program execution. vco see "voltage-controlled oscillator." vector a memory location that contains the address of the beginning of a subroutine written to service an interrupt or reset. voltage-controlled oscillator (vco) a circuit that produces an oscillating output signal of a frequency that is controlled by a dc voltage applied to a control input. waveform a graphical representation in which the amplitude of a wave is plotted against time. wired-or connection of circuit outputs so that if any output is high, the connection point is high. word a set of two bytes (16 bits). write the transfer of a byte of data from the cpu to a memory location. x the lower byte of the index register (h:x) in the cpu08. z the zero bit in the condition code register of the cpu08. the cpu08 sets the zero bit when an arithmetic operation, logical operation, or data manipulation produces a result of $00. f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC708XL36 motorola index 363 index index a accumulator (a) 43, 46 ack1 bit ( irq1 interrupt request acknowledge bit) 312, 314, 318C319 ack2 bit ( irq2 interrupt request acknowledge bit) 312, 316, 318C319 ackk bit (keyboard acknowledge bit) 328 acq bit (acquisition mode bit) 90C91, 100C101, 107 adc instruction 46 add instruction 46 arithmetic/logic unit (alu) 48 auto bit (automatic bandwidth control bit) 91, 98, 100, 104 b baud rate mismatch 252 sci module 278C281 bb[1:0] bits (dma bus bandwidth control bits) 121, 133, 136C137 bcd arithmetic 46 bcfe bit (break clear flag enable bit) 131, 156, 185, 262, 318, 326 bcs bit (base clock select bit) 75, 91, 94, 99, 101, 103C105 bih instruction 315 bil instruction 315 bkf bit (sci break flag bit) 277 branch instructions 45C46 break character 245, 267, 274 break interrupt 66, 82 causes 150 during wait mode 80 effects on cop 152, 310 effects on cpu 49, 152 effects on dma 131, 152 effects on spi 224 effects on tim 152, 185 flag protection during 66 break module break address registers (brkh/l) 131 break signal 162 brk module 149, 156 break address registers (brkh/l) 75, 150, 152C155 break flag control register (bfcr) 156 break status and control register (bscr) 75, 150, 153C154 break status register (bsr) 155 in stop mode 75 in wait mode 75 brka bit (break active bit) 75, 150, 153C154 brke bit (break enable bit) 75, 153C154 bus frequency 12, 42, 92, 97, 186 bw bit (break/wait bit) 75, 153, 156 bwc bit (dma byte/word control bit) 141 bwcx bits (dma byte/word control bits) 120 c c bit (carry/borrow flag) 46C47 ceramic resonator 84 cgm 84, 110 in stop mode 75, 105 in wait mode 75, 105 pll bandwidth control register (pbwc) 90, 98, 100, 104, 107 pll control register (pctl) 75, 94, 98, 103, 105 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . index MC68HC708XL36 364 index motorola pll programming register (ppg) 93, 98, 102 cgmint signal 75, 97, 105 cgmout signal 75, 84, 86, 90, 94, 97, 99, 101, 104C105, 233 cgmrclk signal 86, 89 cgmrdv signal 89 cgmvclk signal 75, 84, 86, 90, 94, 97, 99C100, 104C105 cgmvdv signal 89 cgmxclk signal 58C60, 75C76, 84, 86, 94, 97, 99, 105, 306C307, 309 duty cycle 97 cgmxfc pin 18, 96, 109 cgnd pin 227 cgnd/ev ss pin 18 chxf bits (tim channel interrupt flag bits) 67, 183, 194 chxie bits (tim channel interrupt enable bits) 67, 183, 194C195 chxmax bits (tim maximum duty cycle bits) 183, 198 cli instruction 47 condition code register (ccr) 46, 314 configuration register (config) 39C40, 60, 76, 308C309, 330C331 cop bit (cop reset bit) 60, 307 cop control register (copctl) 307C308 cop counter 76, 305C309 cop module 305, 310 during break interrupt 310 in stop mode 76 in wait mode 76 cop timeout period 39C40, 76, 306, 309 copd (cop disable bit) 40 coprs bit (cop rate select bit) 40 cpha bit (spi clock phase bit) 209, 226, 229 cpol bit (spi clock polarity bit) 229 cpu interrupt external 18, 76, 130 software 49, 150 cpu interrupts dma 122, 138, 146 external 79, 184 masking 46 pll 90C91, 97C98, 104 sci 78, 242, 246, 257, 261, 268, 273 software 66 spi 79, 223, 231 tim 194 tim input capture 177 tim output compare 177 tim overflow 67, 183 cpu registers h register 34 stack pointer 33 crosstalk 95 crystal 75, 84, 86, 97, 105, 108, 162, 306C307 d daa instruction 46 dma module 112, 148 block transfers 135C136, 143, 145C146 destination address registers (d0dh/lCd2dh/l) 120 dma block length registers (d0blCd2bl) 120, 122C123, 132, 141, 146C148 dma bus bandwidth 121, 133C134, 137 dma byte count registers (d0bcCd2bc) 122C123, 132, 137, 141, 146, 148 dma channel control registers (d0cCd2c) 122, 132, 140 dma control register 1 (dc1) 120, 122, 132C133, 138, 146 dma control register 2 (dc2) 121C122, 132, 139 dma destination address registers (d0dh/lCd2dh/l) 122C123, 137, 140, 145, 148 dma latency 122, 132 dma service request priority 136C137 dma source address registers (d0sh/lCd2sh/l) 120, 122C123, 137, 140, 143C144 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . index MC68HC708XL36 motorola index 365 dma status and control register (dsc) 120, 132, 136, 146 in stop mode 76 in wait mode 76, 138 looping transfers 123, 135, 146 transfer sources 122C123, 139, 142 dma service request priority 120 dma service requests sci 242, 246, 257, 268, 273 spi 231 tim 194 tim input capture 177 tim output compare 177 dmap bit (dma priority bit) 76, 120, 130, 136 dmare bit (sci dma receive enable bit) 257, 268, 274 dmas bit (spi dma select bit) 229, 231 dmate bit (sci dma transfer enable bit) 246, 268, 271C273 dmawe bit (dma wait enable bit) 120, 138 dts[2:0] bits (dma transfer source bits) 120, 122, 139, 141 e elat bit (eprom latch control bit) 37C38 electrostatic damage 284 elsxa/b bits (tim edge/level select bits) 182, 196C197 ensci bit (enable sci bit) 241, 264 epgm bit (eprom program control bit) 37C38 epmcpd bit (eprom charge pump disable bit) 37 eprom erasure 36 locations 36 programming 18 programming tools 36 security 12, 36, 158, 169 size 12, 22 eprom control register (epmcr) 37 external crystal 82, 101 external filter capacitor 96, 108C109 external reset 58 f f bus (bus frequency) 92 fe bit (sci framing error bit) 69, 258 fe bit (sci receiver framing error bit) 276 feie bit (sci framing error interrupt enable bit) 69, 258 feie bit (sci receiver framing error interrupt enable bit) 272, 276 flag protection in break mode 66 f nom (nominal center-of-range frequency) 89 f rclk (pll reference clock frequency) 89 f rdv (pll final reference frequency) 89, 108, 110 f vclk (vco output frequency) 89 f vrs (vco programmed center-of-range frequency) 89, 93, 103 h h bit (half-carry flag) 46 i i bit (interrupt mask) 46, 63, 314, 319 i/o port pin termination 284 i/o registers locations 24 idle bit (sci receiver idle bit) 68, 257, 275 idle character 68, 245C246, 264C265 iecx bits (dma cpu interrupt enable bits) 135, 137 ifc[2:0] bits (dma cpu interrupt flag bits) 138 ifcx bits (dma cpu interrupt flag bits) 137, 141, 146 ilad bit (illegal address reset bit) 60C61 ilie bit (sci idle line interrupt enable bit) 68, 257, 268 ilop bit (illegal opcode reset bit) 60C61 ilty bit (sci idle line type bit) 265 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . index MC68HC708XL36 366 index motorola imask1 bit ( irq1 interrupt mask bit) 314, 319 imask2 bit ( irq2 interrupt mask bit) 314, 316, 319 imaskk (keyboard interrupt mask bit) 328 index register (h:x) 44, 63 input capture 67, 172C173, 177, 183, 186, 192, 199, 294 internal address bus 150 internal reset 58 timing 58 interrupt status and control register (iscr) 312 interrupts vector addresses 65 irq module in stop mode 77 in wait mode 77 irq status and control register (iscr) 318 irq1 pin 18, 37C38, 309, 314C315 triggering sensitivity 312 irq2 pin 18, 316 triggering sensitivity 312 irq2f bit ( irq2 interrupt flag) 319 j jump instructions 45 k kbiex bits (keyboard interrupt enable bits) 324, 328 keyboard interrupt enable register (kbier) 328 keyboard interrupt pins 19 keyboard status and control register (kbscr) 327 keyf bit (keyboard flag bit) 327 keyf bit (keyboard interrupt flag bit) 324 l l (vco linear range multiplier) 93 l[2:0] bits (dma loop enable bits) 137 lda instruction 63 literature distribution centers 371 lock bit (lock indicator bit) 90, 98, 100, 104, 107 loops bit (sci loop mode select bit) 264 lvi bit (low-voltage inhibit reset bit) 60 lvi module in stop mode 78 in wait mode 78 lvi status register (lvisr) 330C331 lvi trip voltage 329 lviout bit (lvi output bit) 330C331 lvipwrd bit (lvi power disable bit) 40 lvirst bit (lvi reset bit) 330 lvirstd bit (lvi reset disable bit) 40 lvistop bit (lvi enable in stop mode bit) 40 m m bit (sci character length bit) 241, 245, 265 m6805 compatibility 34 m68hc08 family 12, 41 mode1 bit ( irq1 edge/level select bit) 312, 314, 320 mode2 bit ( irq2 interrupt edge/level select bit) 312, 316, 319 modek bit (keyboard triggering sensitivity bit) 323, 328 modf bit (mode fault error bit) 214 modf bit (spi mode fault bit) 232 monitor commands iread 166 iwrite 166 read 165 readsp 167 run 167 write 165 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . index MC68HC708XL36 motorola index 367 monitor mode 49, 150, 152, 309 alternate vector addresses 161 baud rate 162 commands 158 echoing 162C163 eprom programming 158 monitor rom 22 msxa/b bits (tim mode select bits) 178, 181C183, 195C196 msxb bits (tim mode select bits) 181 n n (vco frequency multiplier) 92C93 n bit (negative flag) 47 neie bit (sci noise error interrupt enable bit) 68, 258, 276 neie bit (sci receiver noise error interrupt enable bit) 272 nf bit (sci noise flag bit) 68, 258, 276 noise 17, 68, 89C90, 95C96, 106, 108C109, 181C182, 258, 276, 278 o object code 12 opcode map 56 or bit (sci receiver overrun bit) 68, 258, 275 ordering information literature distribution centers 371 mfax 372 web server 372 web site 372 orie bit (sci overrun interrupt enable bit) 68, 258 orie bit (sci receiver overrun interrupt enable bit) 272, 275 osc1 pin 18, 96C97 osc2 pin 18, 96C97 oscillator 86, 94, 96, 307 pins 18 stabilization delay 59C60 output compare 67, 172C173, 177C179, 182C183, 186, 192, 199, 294 ovrf bit (overflow bit) 214 ovrf bit (spi overflow bit) 232 p packages qfp 16, 300, 303 sdip 15 parity sci module 69, 258, 264, 266, 272 pe bit (sci parity error bit) 69, 258 pe bit (sci receiver parity error bit) 277 peie bit (sci parity error interrupt enable bit) 69, 258 peie bit (sci receiver parity error interrupt en- able bit) 272, 277 pen bit (sci parity enable bit) 266 phase-locked loop (pll) 75, 84, 86, 88, 92, 94, 96C97, 104C110 acquisition mode 88, 90, 100C101, 106C109 acquisition time 106C110 automatic bandwidth mode 90 lock detector 88, 90, 97 lock time 106, 108C110 loop filter 88, 90, 96 manual bandwidth mode 100 phase detector 88, 108 tracking mode 88, 90, 100, 107, 110 voltage-controlled oscillator (vco) 75, 86, 88, 90, 94, 100, 102C105, 108 pin bit (external reset bit) 58, 61 pllf bit (pll flag bit) 104 pllf bit (pll interrupt flag bit) 98 pllie bit (pll interrupt enable bit) 66, 91, 98 pllon bit (pll on bit) 75, 91, 99, 103, 105 por bit (power-on reset bit) 59, 61 port a 19, 286C287 data direction register a (ddra) 286 port a data register (porta) 286 port b 19, 288C289 data direction register b (ddrb) 288 port b data register (portb) 288 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . index MC68HC708XL36 368 index motorola port c 19, 290C291 data direction register c (ddrc) 290 port c data register (portc) 290 port d 19, 292C293 data direction register d (ddrd) 292 keyboard interrupt enable register (kbicr) 292 port d data register (portd) 292 port e 19, 294, 297 data direction register e (ddre) 296 port e data register (porte) 294 port f 19, 297, 300 data direction register f (ddrf) 299 port f data register (portf) 297 port g 20, 300, 302 data direction register g (ddrg) 301 port g data register (portg) 300 port h 20, 303C304 data direction register h (ddrh) 303 port h data register (porth) 303 power supply 108 bypassing 17 pins 17 program counter (pc) 45, 49, 152, 315C316, 323 ps[2:0] bits (tim prescaler select bits) 177, 189 pshh instruction 47 pty bit (sci parity bit) 266 pulh instruction 47 pulse-width modulation 172 pulse-width modulation (pwm) 179C181, 186, 192 duty cycle 180, 183, 198 frequency 180 initialization 182 r r8 bit (sci received bit 8) 271 ram 33C34, 158 size 12, 22 stack ram 45 re bit (sci receiver enable bit) 269 reset cop 58, 61, 76, 305, 309 external 61 external reset pin ( rst) 18 illegal address 58, 60C61 illegal opcode 58, 60C61 internal 18, 58C59, 308 lvi 58 por 58C59, 61 power-on 307 reset status register (rsr) 58, 60C61, 307 rpf bit (sci reception in progress flag bit) 278 rst pin 58, 61, 307 rti instruction 47, 49, 63, 150 rwu bit (sci receiver wake-up bit) 269 s sbk bit (sci send break bit) 245, 270 sci module 236, 281 baud rate 237, 278 character format 266 dma service requests 121 error conditions 68, 258 framing error 252, 276 i/o pins 263 in stop mode 78 in wait mode 78 noise error 276 overrun error 272 parity 266, 272, 277 parity error 69, 258 sci baud rate register (scbr) 279 sci control register 1 (scc1) 241, 245, 264 sci control register 2 (scc2) 68, 241, 245C246, 257, 267, 273 sci control register 3 (scc3) 68, 241, 246, 257C258, 268, 270, 273 sci data register (scdr) 68, 241C242, 246, 249, 257C258, 271, 274, 277C278 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . index MC68HC708XL36 motorola index 369 sci status register 1 (scs1) 68, 242, 246, 249, 257C258, 264, 273 sci status register 2 (scs2) 277 scp1Cscp0 bits (sci baud rate prescaler bits) 279 scrf bit (sci receiver full bit) 68, 249, 257, 268, 274 scrie bit (sci receiver interrupt enable bit) 68, 257, 268, 274 scte bit (sci transmitter empty bit) 68, 242, 246, 264, 268, 273 sctie bit (sci transmitter interrupt enable bit) 68, 242, 246, 268, 273 sdc[3:0] bits (dma source/destination ad- dress control bits) 120, 140 simoscen signal 86, 96 spe bit (spi enable bit) 230 spi module 201, 234 baud rate 230, 233 dma service requests 121 i/o pins 225 in stop mode 79, 224 in wait mode 79 mode fault error 214, 232 overflow error 214, 232 receive data register 67, 206C207, 215, 221, 228, 230C232, 234 slave select pin 214, 230 spi control register (spcr) 225, 228, 231 spi data register 214, 231 spi data register (spdr) 206, 234 spi status and control register 232 spi status and control register (spscr) 206, 214, 230C231 transmit data register 67, 206C207, 209, 211, 213, 224, 230, 232, 234 spmstr bit (spi master mode bit) 205, 207, 225, 229 spr[0:1] bits (spi baud rate select bits) 206 spr1[1:0] bits (spi baud rate select bits) 233 sprf bit (spi receiver full bit) 67, 206C207, 213, 228, 230C231 sprie bit (spi receiver interrupt enable bit) 67, 228, 231 spte bit (spi transmitter empty bit) 67, 206, 213, 229C230, 232 spte bit (spi transmitter enable bit) 233 sptie bit (spi transmitter interrupt enable bit) 67, 230, 232 spwom bit (spi wired-or mode bit) 225, 230 ssrec bit (short stop recovery bit) 40, 82 stack pointer (sp) 33, 44 stack ram 33, 45 start bit 162 sci data 242, 245, 249, 265, 270, 278 stop bit sci data 69, 242, 245C246, 252C254, 256, 258, 265, 276 stop bit (stop enable bit) 40, 60, 76, 309 stop instruction 74C79, 99, 105, 130, 153, 184, 223C224, 261, 307, 309, 332 enabling 39 stop mode 75C76, 78C79, 130, 153, 184, 224, 261, 278, 309, 332 stop mode recovery time 39 swi instruction 49, 66, 150, 152 swi[7:0] bits (dma software initiate bits) 139 t t8 bit (sci transmitted bit 8) 271 t8 bit (transmitted sci bit 8) 241 tc bit (sci transmission complete bit) 264, 268, 274 tc bit (transmission complete bit) 68, 246 tcie bit (sci transmission complete interrupt enable bit) 268, 274 te bit (sci transmitter enable bit) 246, 269 te bit (transmitter enable bit) 241 tecx bits (dma transfer enable bits) 77, 120C121, 135C136 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . index MC68HC708XL36 370 index motorola tim 172, 199 clock input pin (tclk) 177, 186 dma service requests 121 in stop mode 184 in wait mode 184 prescaler 177 tim channel registers (tch0h/lCtch3h/l) 177C181, 186, 197, 199 tim channel registers (tchxh/l) 177 tim channel status and control registers (tsc0Ctsc3) 178, 181, 192 tim counter modulo registers (tmodh/l) 67, 180, 183, 192 tim counter modulo registers (tmodh:tmodl) 182 tim counter registers (tcnth/l) 191, 194 tim counter registers (tcnth:tcntl) 191 tim dma select register (tdma) 183, 190, 195 tim modulo registers (tmodh:tmodl) 173 tim status and control register (tsc) 67, 177, 182C183, 188, 196 tim counter 173, 185 tof bit (tim overflow bit) 67, 183 tof bit (tim overflow flag bit) 188, 192 toie bit (tim overflow interrupt enable bit) 67, 183, 188 tovx (tim toggle on overflow bits) 183 tovx bits (tim overflow bits) 182 tovx bits (tim toggle on overflow bits) 183, 198 trst bit (tim reset bit) 182, 189, 191, 196 tstop bit (tim stop bit) 182, 189, 196 txinv bit 265 txinv bit (sci transmit inversion bit) 246, 265 u ultraviolet light 36 user vectors 22 addresses 32 v v bit (overflow flag) 46 v dd pin 17 v dda pin 18, 96, 108C109 voltage-controlled oscillator (vco) 92, 97, 99 vrs[7:4] bits (vco range select bits) 103 v ss pin 17 w wait instruction 74, 76, 130, 138, 153, 184, 223, 261, 309, 332 wait mode 75C76, 78C79, 130, 153, 184, 189, 223, 261, 309, 332 exit by break interrupt 155 wake bit (sci wake-up condition bit) 265 web server 372 web site 372 x xld bit (crystal loss detect bit) 101 z z bit (zero flag) 47 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC708XL36 motorola literature updates 371 literature updates literature updates this document contains the latest data available at publication time. for updates, contact one of the centers listed below: literature distribution centers order literature by mail or phone. usa/europe motorola literature distribution p.o. box 20912 phoenix, arizona 85036 phone 1 800 441-2447 or 602 303-5454 japan nippon motorola ltd. tatsumi-spd-jldc toshikatsu otsuki 6f seibu-butsuryu center 3-14-2 tatsumi koto-ku tokyo 135, japan phone 03-3521-8315 hong kong motorola semiconductors h.k. ltd. 8b tai ping industrial park 51 ting kok road tai po, n.t., hong kong phone 852-26629298 f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . literature updates MC68HC708XL36 372 literature updates motorola mfax to access this worldwide faxing service call or contact by electronic mail: rmfax0@email.sps.mot.com touch-tone 602-244-6609 or, on the http://design-net.com home page, select the mfax icon. obtain a fax of complete, easy-to-use mfax instructions by entering your fax number and then pressing the 1 key. motorola sps world marketing world wide web server use the internet to access motorolas world wide web server. use the following url: http://design-net.com csic microcontroller divisions web site directly access the csic microcontroller divisions web site with the following url: http://design-net.com/csic/csic_home.html f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . MC68HC708XL36 technical data customer response survey to make m68hc08 documentation as clear, complete, and easy to use as possible, we need your comments. please complete this form and return it by mail, or fax it to 512-891-3236. 1. how do you rate the quality of this document? 2. what is your intended use for this document? 3. does this document help you to perform your job? 4. are you able to easily find the information you need? 5. does each section of the document provide you with enough information? high low high low organization tables readability table of contents accuracy page size/binding figures overall impression comments: device selection for new application other please specify: system design training ye s n o comments: ye s n o comments: yes no yes no introduction monitor rom memory timer interface module ram spi module eprom sci module con?guration register i/o ports cpu cop module resets and interrupts irq module low-power modes keyboard interrupt module clock generator module lvi module direct memory access module speci?cations break module glossary index 6. what would you like us to do to improve this document? f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . first: cut along this line to remove motorola 6501 william cannon drive west mail stop oe17 austin, texas 78735-8598 attn: csic publications department second: fold back along this line please supply the following information (optional). name: ___________________________________________________ company name: ___________________________________________ title: ____________________________________________________ address: _________________________________________________ city: _____________________________state: _____zip:__________ phone number: ____________________________________________ csic microcontroller division f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . f r e e s c a l e s e m i c o n d u c t o r , i freescale semiconductor, inc. f o r m o r e i n f o r m a t i o n o n t h i s p r o d u c t , g o t o : w w w . f r e e s c a l e . c o m n c . . . how to reach us: usa/europe/locations not listed: motorola literature distribution; p.o. box 20912; phoenix, arizona 85036.1-800-441-2447 or 602-303-5454 mfax: rmfax0@email.sps.mot.com C touchtone 602-244-6609 internet: http://design-net.com japan: nippon motorola ltd.; tatsumi-spd-jldc, 6f seibu-butsuryu-center, 3-14-2 tatsumi koto-ku, tokyo 135, japan. 03-81-3521-8315 asia/pacific: motorola semiconductors h.k. ltd.; 8b tai ping industrial park, 51 ting kok road, tai po, n.t., hong kong. 852-26629298 freescale semiconductor, i freescale semiconductor, inc. for more information on this product, go to: www.freescale.com nc... |
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